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AT77C104B Datasheet(PDF) 3 Page - ATMEL Corporation |
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AT77C104B Datasheet(HTML) 3 Page - ATMEL Corporation |
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3 / 36 page  3 AT77C104B 5347B–BIOM–08/04 Figure 1. Typical Application The pull-up must be implemented for the master controller. The noise should be lower than 30 mV peak to peak on VDDA. Figure 2. Pin Description The TESTA pin is only used for testing and debugging. The SCANEN pin is not used in the final application and must be connected to ground. Warning : SSS and FSS must never be low at the same time. When both SSS and FSS equal 0, the chip switches to scan test mode. With the SPI protocol, this configuration is not possible as only one slave at a time can be selected. However, this configuration works when debugging the system. TESTA IRQ TPP MISO VDDD MOSI SCK GNDD SSS VDDA FSS SCANEN GNDA FPL RST VDDA 10 k Ω 10 k Ω VDDD VDDD 10µF GND NC 10µ GND VDDD F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NC NC NC NC GNDD GNDA VDDD VDDA SCK TESTA MOSI TPP MISO SCANEN SSS IRQ FSS RST FPL |
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