TPA3138D2PWPR datasheet(3/36 Pages) TI1

3 / 36 page

PVCCL

SD/FAULT

PVCCL

LINP

BSPL

LINN

OUTPL

GAIN_SEL

GND

MODE_SEL

OUTNL

AVCC

BSNL

GND

BSNR

GVDD

OUTNR

PLIMIT

GND

RINN

OUTPR

RINP

BSPR

PVCCR

AGND

PVCCR

Not to scale

Thermal

Pad

TPA3138D2

www.ti.com

SLOS993A – MARCH 2018 – REVISED JUNE 2018

Product Folder Links: TPA3138D2

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5 Device Comparison Table

Product

Supply Voltage

Modulation Scheme

Package

Rdson

Gain

Inductor Free

TPA3138D2

3.5-V to 14.4-V

BD, 1SPW

HTSSOP-28

180-mΩ

20-dB, 26-dB

YES

TPA3110D2

8-V to 26-V

HTSSOP-28

240-mΩ

20-dB, 26-dB, 32-dB, 36-dB

TPA3136D2

4.5-V to 14.4-V

HTSSOP-28

240-mΩ

26-dB

YES

TPA3136AD2

8-V to 14.4-V

HTSSOP-28

240-mΩ

26-dB

YES

(1)

I = Input, O = Output, IO = Input and Output, P = Power

6 Pin Configuration and Functions

PWP Package

28-Pin HTSSOP

(Top View)

Pin Functions

I/O/P(1)

DESCRIPTION

NAME

NO.

–

No Connect Pin. Can be shorted to PVCC or shorted to GND or left open.

SD/FAULT

TTL logic levels with compliance to AVCC. Shutdown logic input for audio amp (LOW , outputs Hi-Z;

HIGH , outputs enabled). General fault reporting including Over-Temp, Over-Current, DC Detect.

SD/FAULT= High, normal operation, SD/FAULT= Low, fault condition Device will auto-recover once

the OT/OC/DC Fault has been removed.

LINP

Positive audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode.

LINN

Negative audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode.

GAIN_SEL

Gain select least significant bit. TTL logic levels with compliance to AVDD. Low = 20 dB Gain, High =

26 dB Gain, Floating = 26 dB Gain.

TPA3138D2PWPR Datasheet(PDF) 3 Page - Texas Instruments

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