AD9548BCPZ datasheet(92/111 Pages) AD

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AD9548

Data Sheet

Table 117. Fractional Feedback Divider—Profile 3

Address

Bits

Bit Name

Description

0x06D8

[7:0]

V, Bits[7:0]

0x06D9

[7:4]

U, Bits[3:0]

[3:2]

Unused

[1:0]

V, Bits[9:8]

0x06DA

[7:6]

Unused

[5:0]

U, Bits[9:4]

Table 118. Lock Detectors—Profile 3

Address

Bits

Bit Name

Description

0x06DB

[7:0]

Phase lock threshold (units determined by Register 0x06B2[7])

Phase lock threshold, Bits[7:0]

0x06DC

[7:0]

Phase lock threshold, Bits[15:8]

0x06DD

[7:0]

Phase lock fill rate

Phase lock fill rate, Bits[7:0]

0x06DE

[7:0]

Phase lock drain rate

Phase lock drain rate, Bits[7:0]

0x06DF

[7:0]

Frequency lock thresh-old (in picoseconds)

Frequency lock threshold, Bits[7:0]

0x06E0

[7:0]

Frequency lock threshold, Bits[15:8]

0x06E1

[7:0]

Frequency lock threshold, Bits[23:16]

0x06E2

[7:0]

Frequency lock fill rate

Frequency lock fill rate, Bits[7:0]

0x06E3

[7:0]

Frequency lock drain rate

Frequency lock drain rate, Bits[7:0]

0x06E4 to 0x06FF

[7:0]

Unused

Profile 4 (Register 0x0700 to Register 0x0731) is identical to Profile 0 (Register 0x0600 to Register 0x0631).

Profile 5 (Register 0x0732 to Register 0x077F) is identical to Profile 1 (Register 0x0632 to Register 0x067F).

Profile 6 (Register 0x0780 to Register 0x07B1) is identical to Profile 2 (Register 0x0680 to Register 0x06B1).

Profile 7 (Register 0x07B2 to Register 0x07FF) is identical to Profile 3 (Register 0x06B2 to Register 0x06FF).

OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10)

Table 119. General Power-Down

Address

Bits

Bit Name

Description

0x0A00

[7]

Reset sans reg map

Reset internal hardware but retain programmed register values.

0 (default) = normal operation.

1 = reset.

[6]

Unused

[5]

SYSCLK power-down

Place SYSCLK input and PLL in deep sleep mode.

0 (default) = normal operation.

1 = power-down.

[4]

Reference power-down

Place reference clock inputs in deep sleep mode.

0 (default) = normal operation.

1 = power-down.

[3]

TDC power-down

Place the time-to-digital converter in deep sleep mode.

0 (default) = normal operation.

1 = power-down.

[2]

DAC power-down

Place the DAC in deep sleep mode.

0 (default) = normal operation.

1 = power-down.

[1]

Dist power-down

Place the clock distribution outputs in deep sleep mode.

0 (default) = normal operation.

1 = power-down.

[0]

Full power-down

Place the entire device in deep sleep mode.

0 (default) = normal operation.

1 = power-down.

Rev. G | Page 92 of 111

AD9548BCPZ Datasheet(PDF) 92 Page - Analog Devices

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