AD9558BCPZ datasheet(39/105 Pages) AD

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Data Sheet

AD9558

Rev. C | Page 39 of 105

OUTPUT PLL (APLL)

A diagram of the output PLL (APLL) is shown in Figure 42.

LF CAP

VCO2

3.35GHz TO 4.05GHz

PFD

FROM DPLL

TO CLOCK

DISTRIBUTION

INTEGER DIVIDER

OUTPUT PLL DIVIDER (APLL)

÷N2

LF_VCO2

Figure 42. Output PLL Block Diagram

The APLL provides the frequency upconversion from the DPLL

output to the 3.35 GHz to 4.05 GHz range, while also providing

noise filtering on the DPLL output. The APLL reference input is

the output of the DPLL. The feedback divider is an integer divider.

The loop filter is partially integrated with the one external 6.8 nF

capacitor. The nominal loop bandwidth for this PLL is 250 kHz,

with 68°of phase margin.

The frequency wizard that is included in the evaluation software

configures the APLL, and the user does not need to make

changes to the APLL settings. However, there may be special cases

where the user may want to adjust the APLL loop bandwidth to

meet a specific phase noise requirement. The easiest way to change

the APLL loop bandwidth is to adjust the APLL charge pump

current in Register 0x0400. There is sufficient stability (68° of

phase margin) in the APLL default settings to permit a broad

range of adjustment without causing the APLL to be unstable.

Contact Analog Devices directly if more detail is needed.

Calibration of the APLL must be performed at startup and

when the nominal input frequency to the APLL changes by

more than ±100 ppm, although the APLL maintains lock

over voltage and temperature extremes without recalibration.

Calibration centers the dc operating voltage at the input to the

APLL VCO.

APLL calibration at startup can be accomplished during initial

this data sheet.

To recalibrate the APLL VCO after the chip has been running,

the user must first input the new settings (if any). Ensure that

the system clock is still locked and stable, and that the DPLL is

in free run mode with the free run tuning word set to the same

output frequency that is used when the DPLL is locked.

Take the following steps to calibrate the APLL VCO:

1. Ensure that the system clock is locked and stable.

2. Ensure that the DPLL is in user free run mode

(Register 0x0A01[5] = 1b), and that the free run tuning

word is set.

3. Write Register 0x0405 = 0x20.

4. Write Register 0x0005 = 0x01.

5. Write Register 0x0405 = 0x21.

6. Write Register 0x0005 = 0x01.

Monitor the APLL status using Bit 2 in Register 0x0D01.

AD9558BCPZ Datasheet(PDF) 39 Page - Analog Devices

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