AD9558BCPZ datasheet(13/105 Pages) AD

13 / 105 page

Data Sheet

AD9558

Rev. C | Page 13 of 105

SERIAL PORT SPECIFICATIONS—SPI MODE

Table 15.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

µA

Input Logic 0 Current

100

µA

Input Capacitance

SCLK

Internal 30 kΩ pull-down resistor

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

200

µA

Input Logic 0 Current

µA

Input Capacitance

SDIO

As an Input

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

µA

Input Logic 0 Current

µA

Input Capacitance

As an Output

Output Logic 1 Voltage

DVDD3 − 0.6

1 mA load current

Output Logic 0 Voltage

0.4

1 mA load current

SDO

Output Logic 1 Voltage

DVDD3 − 0.6

1 mA load current

Output Logic 0 Voltage

0.4

1 mA load current

TIMING

SCLK

Clock Rate, 1/tCLK

MHz

Pulse Width High (tHIGH)

Pulse Width Low (tLOW)

SDIO to SCLK Setup (tDS)

SCLK to SDIO Hold (tDH)

SCLK to Valid SDIO and SDO (tDV)

CS to SCLK Setup (tS)

CS to SCLK Hold (tC)

CS Minimum Pulse Width High

AD9558BCPZ Datasheet(PDF) 13 Page - Analog Devices

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