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MON35W42 Datasheet(PDF) 30 Page - SMSC Corporation |
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MON35W42 Datasheet(HTML) 30 Page - SMSC Corporation |
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30 / 60 page ![]() 30 Reserved Register ! ! ! ! Index 45h Chassis Clear Register -- Index 46h Register Location: 46h Power on Default Value <7:0> = 00000000 binary Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear Bit 7: Set to 1, clear Chassis Intrusion event. This bit self clears after clearing Chassis Intrusion event. Bit 6-0:Reserved. This bit should be set to 0. VID/Fan Divisor Register ! ! ! ! Index 47h Register Location: 47h Power on Default Value <7:4> is 0101, <3:0> is mapped to VID<3:0> Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 VID0 VID1 VID2 VID3 FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1 Bit 7-6: FAN2 Speed Control. Bit 5-4: FAN1 Speed Control. Bit 3-0: The VID <3:0> inputs Note: Please refer to Bank0 CR[5Dh] , Fan divisor table. |
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