MP6538 – 100V, THREE-PHASE, BLDC MOTOR PRE-DRIVER WITH HALL SIGNAL INTERFACE

MP6538 Rev. 1.01

www.MonolithicPower.com

11

4/20/2018

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© 2018 MPS. All Rights Reserved.

OPERATION

The MP6538 is a three-phase, BLDC motor

pre-driver that can drive three half-bridges with

a 0.8A source and 1A sink current capability.

The MP6538 supports operation up to 100V.

The MP6538 features a low-power sleep mode,

which disables the device and draws very low

supply current.

The MP6538 provides several flexible functions,

such as adjustable dead-time control and over-

current protection (OCP), which allow the

device to cover a wide range of applications.

Power-Up Sequence

The power-up sequence is initiated by the

application of voltage to VIN and the voltage

present on VREG. Usually, VREG is supplied

by the internal LDO regulator connected to VIN,

but it is also possible to drive VREG from

another power source.

To initiate a power-up, VIN must be above

~4.5V, and VREG must be above the VREG

under-voltage lockout (UVLO) threshold of 7.4V.

If VREG is supplied by the internal LDO

regulator, this means that VIN must be at about

8V before the part starts to power up. After

VREG exceeds the VREG UVLO threshold, the

MP6538 sequentially turns on each low-side

MOSFET (LS-FET) in succession to charge the

bootstrap capacitors.

The power-up process takes between 1ms and

2ms, after which the MP6538 responds to logic

inputs and drives the outputs.

Input Logic

Driving nSLEEP low puts the device into a low-

power sleep state. In this state, all internal

circuits are disabled. All inputs are ignored

when nSLEEP is active low. When waking up

from sleep mode, approximately 1ms of time

must

pass

before

issuing

a

pulse-width

modulation (PWM) command to allow the

internal circuitry time to stabilize.

The commutation logic is determined by three

Hall-element inputs spaced at 120°. The PWM,

DIR, and nBRAKE inputs are used to control

motor speed, position, and torque (see Table 1).

Table 1: Input Logic Truth Table

PWM

nBRAKE

Mode of Operation

0

1

PWM chop mode, the load

current decays

0

0

Brake mode

– all low-side

gates on

1

1

Selected drivers on

1

0

Brake mode

– all low-side

gates on

Refer to Table 2 for the commutation table with

nBRAKE = 1. If nBRAKE = 0, the braking

function is active, and all low-side gates are on.

nFAULT

nFAULT reports to the system when a fault

condition

occurs,

such

as

over-current

protection

(OCP)

or

over-temperature

protection (OTP). nFAULT is an open-drain

output type and is driven low when a fault

condition occurs. If the fault condition is

released, nFAULT is pulled up to a high level by

an external pull-up resistor.

Current-Sense Amplifier

An integrated current-sense amplifier amplifies

the voltage on LSS (relative to GND) by a factor

of 20. This voltage is output to CSO.

The

current-sense

amplifier

only

sources

current. An external capacitor of 1nF (minimum)

must be connected from CSO to ground for

stability.

During the PWM on time, current flowing

through

the

output

MOSFETs

also

flows

through the shared low-side current sense

resistor, generating a voltage that is amplified

by the current sense amplifier, which charges

the external capacitor on CSO. During the

PWM off time, current recirculates through the

LS-FETs, and does not pass through the sense

resistor, so there is zero voltage across it.

During this time, the capacitor discharges

through

the

internal

feedback

resistor

(approximately 450k

Ω) and also through any

external resistor to ground. Select an external

resistor and capacitor to provide a filter to hold

the value of the current through the PWM off

time. Any external resistor used should be 1k

Ω

or larger.