MP6538 – 100V, THREE-PHASE, BLDC MOTOR PRE-DRIVER WITH HALL SIGNAL INTERFACE

MP6538 Rev. 1.01

www.MonolithicPower.com

12

4/20/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2018 MPS. All Rights Reserved.

Table 2: Commutation Table (nBRAKE = 1)

Logic Inputs

Driver Outputs

Motor Terminals

HA

HB

HC

DIR

GLA

GLB

GLC

GHA

GHB

GHC

SHA

SHB

SHC

1

0

1

1

/PWM

0

1

PWM

0

0

H

Z

L

1

0

0

1

0

/PWM

1

0

PWM

0

Z

H

L

1

1

0

1

1

/PWM

0

0

PWM

0

L

H

Z

0

1

0

1

1

0

/PWM

0

0

PWM

L

Z

H

0

1

1

1

0

1

/PWM

0

0

PWM

Z

L

H

0

0

1

1

/PWM

1

0

PWM

0

0

H

L

Z

1

0

1

0

1

0

/PWM

0

0

PWM

L

Z

H

1

0

0

0

0

1

/PWM

0

0

PWM

Z

L

H

1

1

0

0

/PWM

1

0

PWM

0

0

H

L

Z

0

1

0

0

/PWM

0

1

PWM

0

0

H

Z

L

0

1

1

0

0

/PWM

1

0

PWM

0

Z

H

L

0

0

1

0

1

/PWM

0

0

PWM

0

L

H

Z

Over-Current Protection (OCP) / Current

Regulation

The voltage across each LS-FET is monitored

by a comparator in the MP6538 to turn the

device off in the event of an over-current

condition. The over-current shutdown voltage

threshold

level

is

programmable

through

OCREF by applying an external reference

voltage with a DAC or resistor divider. When

VDS of the MOSFET exceeds OCREF, CSO is

pulled

to

~6V

internally.

Whenever

CSO

exceeds 3.5V, an OCP event is detected, and

all output MOSFETs are turned off. nFAULT is

driven active low.

Once the current through the LS-FETs and the

sense resistor stops, the CSO voltage is no

longer driven and starts to fall at a rate

determined by the external capacitor and

resistor. When the voltage falls below 2.9V, the

output MOSFETs are re-enabled, and nFAULT

is inactive.

The resulting off time is set by the value of the

external capacitor and the internal feedback

resistor in parallel with the external resistor (if

used).

The off time generated when CSO reaches

3.5V can be approximated with Equation (1):

(1)

The off time generated when VDS exceeds

OCREF is longer since CSO is pulled to 6V and

must decay to 2.9V for the outputs to be re-

enabled.

This

off

time

can

be

approximated

with

Equation (2):

(2)

Where C is the capacitance from CSO to

ground, and R is the total resistance from CSO

to ground, comprised of the internal feedback

resistor (~450k

Ω) in parallel with any external

resistor to ground.

This feature can be used for current regulation

to limit the stall/start-up current of a motor,

either by using an external current sense

the LS-FET.

In addition to low-side current monitoring, a

circuit monitors the output and triggers a fault

condition of the output, driving it high, but it will

not rise above ~4.5V. This provides protection

against a short to ground, which would not be

detected by low-side current sensing. If this

occurs, the MP6538 enters a latched fault state

and disables all outputs. The MP6538 remains

latched off until it is reset by nSLEEP or UVLO.

Gate Drive Voltage Regulator

To generate a voltage to drive the external

MOSFET gates, a linear regulator is integrated

into the MP6538.

If current over about 5mA is needed (to drive

the high gate charge MOSFETs at a high

switching

frequency),

an

external

NPN

transistor (and optionally also a resistor) must

be used to remove power dissipation from the

IC.