MP6538 – 100V, THREE-PHASE, BLDC MOTOR PRE-DRIVER WITH HALL SIGNAL INTERFACE

MP6538 Rev. 1.01

www.MonolithicPower.com

13

4/20/2018

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For low current applications, LDO is connected

to

VREG

directly.

For

higher

current

requirements, an NPN transistor is used (see

Figure 2).

VREG

LDO

Regulator

VIN

LDO

VIN

VIN

optional

Figure 2: High-Current Configuration of the LDO

If desired, an appropriate gate-drive supply

voltage can be supplied directly to VREG from

an external supply. In this case, connect only

the capacitor to LDO. VIN must still be

connected to the motor supply voltage.

OCP Deglitch Time

There is usually a current spike during the

switching transition due to the body diode’s

reverse-recovery

current

or

the

distributed

inductance or capacitance. This current spike

requires filtering to prevent it from erroneously

triggering OCP and shutting down the external

(which is also the minimum on time for the

MOSFET) blanks the output of the VDS monitor

when the outputs are switched.

Charge Pump and Bootstrap

Normally, the high-side gate-drive voltage is

generated from bootstrap capacitors connected

between

SHx

and

BSTx.

The

bootstrap

capacitor is charged whenever the LS-FET is

turned on.

If the output is held at a high state for a long

period

of

time,

the

bootstrap

capacitor

discharges slowly. This eventually results in

gate driver loss for the high-side MOSFET (HS-

FET).

To prevent this, an internal charge pump

generates a voltage to maintain the bootstrap

capacitor charge.

The bootstrap voltage is monitored by an

under-voltage detection circuit. If any bootstrap

voltage falls below the VBST UVLO voltage, the

part initiates a new power-up sequence.

Dead-Time Adjustment

To prevent shoot-through in any phase of the

bridge, it is necessary to insert a dead time

the next complementary turn-on event. The

dead time for all three phases is set by a single

ground using Equation (3):

(3)

If DT is tied to GND directly, an internal

minimum dead time of 30ns is applied. Leave

DT open to generate a 6µs dead time.

VREG and VIN UVLO Protection

If at any time the voltage on VREG falls below the

VREG UVLO threshold voltage, the outputs are

disabled, and the nFAULT signal is asserted.

Operation resumes with a bootstrap refresh when

VREG rises above the UVLO threshold.

If the voltage on VIN falls below the VIN UVLO

threshold voltage, all circuitry in the device is

disabled,

and

the

internal

logic

is

reset.

nFAULT is not be asserted. Operation resumes

when VREG rises above the UVLO threshold.

Thermal Shutdown

If the die temperature exceeds safe limits, the

MP6538 enters a latched fault state similar to

an OCP event, and nFAULT is driven low. Only

nSLEEP or UVLO can unlatch the device from

an OTP fault lockout.