ACE25QC128G datasheet(21/56 Pages) ACE

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ACE25QC128G

128M BIT SPI NOR FLASH

VER 1.1

Write Enable for Volatile Status Register (50H)

See Figure 6, the non-volatile Status Register bits can also be written to as volatile bits.. This gives more

flexibility to change the system configuration and memory protection schemes quickly without waiting for

the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits.

Write Enable for Volatile Status Register instruction will not set the Write Enable Latch bit, it is only valid for

the Write Status Registers instruction to change the volatile Status Register bit values.

Read Instructions

Read Data (03H)

See Figure 7, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit

being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out

on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is

automatically incremented to the next higher address after each byte of data is shifted out allowing for a

continuous stream of data. This means that the entire memory can be accessed with a single command as

long as the clock continues. The command is completed by driving /CS high. The whole memory can be

read with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an

Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in

progress.

Figure 5. Write Status Register Sequence Diagram

Figure 7. Read Data Bytes Sequence Diagram

Figure 6. Write Enable for Volatile Status Register

ACE25QC128G Datasheet(PDF) 21 Page - ACE Technology Co., LTD.