ACE25QC128G datasheet(35/56 Pages) ACE

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ACE25QC128G

128M BIT SPI NOR FLASH

VER 1.1

Erase Security Registers (44H)

The ACE25QC128G provides three 256-byte Security Registers which can be erased and programmed

individually. These registers may be used by the system manufacturers to store security and other

important information separately from the main memory array.

See Figure 27, the Erase Security Registers instruction is similar to Sector/Block Erase instruction. A Write

Enable instruction must previously have been executed to set the Write Enable Latch bit.

The Erase Security Registers instruction sequence: /CS goes low sending Erase Security Registers

instruction /CS goes high. /CS must be driven high after the eighth bit of the instruction code has been

latched in otherwise the Erase Security Registers instruction is not executed. As soon as /CS is driven high,

the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security

Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress

(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0

when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is

reset. The Security Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security

registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security

Registers instruction will be ignored.

Address

A23-A16

A15-A12

A11-A8

A7-A0

Security Registers 1

00H

0001

0000

Byte Address

Security Registers 2

00H

0010

0000

Byte Address

Security Registers 3

00H

0011

0000

Byte Address

Figure 27. Erase Security Registers instruction Sequence Diagram

ACE25QC128G Datasheet(PDF) 35 Page - ACE Technology Co., LTD.