ACE25QC128G datasheet(31/56 Pages) ACE

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ACE25QC128G

128M BIT SPI NOR FLASH

VER 1.1

Read JEDEC ID (9FH)

The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of

device identification. The device identification indicates the memory type in the first byte, and the memory

capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in

progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction

should not be issued while the device is in Deep Power-Down Mode.

See Figure 21, The device is first selected by driving /CS to low. Then, the 8-bit instruction code for the

instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being

shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The

JEDEC ID instruction is terminated by driving /CS to high at any time during data output. When /CS is

driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be

selected, so that it can receive, decode and execute instructions.

Read Unique ID Number (4Bh)

The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to

each ACE25QC128G device. The ID number can be used in conjunction with user software methods to

help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS

pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After which, the

64-bit ID is shifted out on the falling edge of SCLK as shown in Figure 22.

Figure 21. JEDEC ID Sequence Diagram

Figure 22. JEDEC ID Sequence Diagram

ACE25QC128G Datasheet(PDF) 31 Page - ACE Technology Co., LTD.