DAC5686IPZP datasheet(37/46 Pages) TI

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fullscale

16 V

extio

biasj

(GAINCODE ) 1)

B 1 *

FINEGAIN

3072

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

daca_offset[7:0]: The lower 8 bits of the DACA offset

MSB

LSB

daca_gain[7:0]

daca_gain[7:0]: The lower 8 bits of the DACA gain control register. These lower 8 bits are for fine gain control.

This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4%

range.

MSB

LSB

daca_offset[10:8]

sleepa

daca_gain[11:8]

daca_offset[10:8]: The upper 3 bits of the DACA _offset

sleepa: When asserted, DACA is put into the sleep mode.

daca_gain[11:8]: Coarse gain control for DACA; the full-scale output current is:

where GAINCODE is the decimal equivalent of daca_gain [11:8] {0

…15} and the FINEGAIN is daca_gain [1:0] as

2s complement [–127

…128].

MSB

LSB

dacb_offset[7:0]

dacb_offset[7:0]: The lower 8 bits of the DACB offset

MSB

LSB

dacb_gain[7:0]

dacb_gain[7:0]: The lower 8 bits of the DACB gain control register. These lower 8 bits are for fine gain control.

This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4%

range.

MSB

LSB

dacb_offset[10:8]

sleepb

dacb_gain[11:8]

DAC5686IPZP Datasheet(PDF) 37 Page - Texas Instruments

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