DAC5686IPZP datasheet(24/46 Pages) TI

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CLK2

CLK1

D[0:15]

∆ < talign

T0002-01

PLLVDD

PLLGND

CLKGND

CLKVDD

pfd

Charge

Pump

vco

clk_16x

DAC

Sample

Clock

D[15:0]

DIV[1:0]

PLLVDD

SEL[1:0]

PLLVDD

PLLLOCK

LPF

Data

clk_2x

clk_1x

clk_4x

clk_8x

CLK1

CLK1C

Clk Buffer

CLK2

CLK2C

Clk Buffer

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

Figure 26. DAC and Data Clock Mode

The CDC7005 from Texas Instruments is recommended for providing phase-aligned clocks at different

frequencies for this application.

Table 3 provides a summary of the clock configurations with corresponding data rate ranges.

Figure 27. Clock-Generation Architecture

Table 3. Clock-Mode Configuration

CLOCK MODE

PLLVDD

DIV[1:0]

SEL[1:0]

DATA RATE (MSPS)

PLLLOCK PIN FUNCTION

Non-interleaved input data; internal PLL off; DA[15:0] data rate matches DB[15:0] data rate.

External 2

0 V

DC to 160

External clk2/clk2c clock

÷ 2

External 4

0 V

DC to 125

External clk2/clk2c clock

÷ 4

External 8

0 V

DC to 62.5

External clk2/clk2c clock

÷ 8

External 16

0 V

DC to 31.25

External clk2/clk2c clock

÷ 16

External dual clock 2

0 V

DC to 160

None - held low

External dual clock 4

0 V

DC to 125

None - held low

DAC5686IPZP Datasheet(PDF) 24 Page - Texas Instruments

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