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DS2109 Datasheet(PDF) 10 Page - Dallas Semiconductor |
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DS2109 Datasheet(HTML) 10 Page - Dallas Semiconductor |
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10 / 10 page ![]() The chamfer on the body is optional. If it is not present, a termi- nal 1 identifier must be positioned so that 1/2 or more of its area is contained in the hatched zone. DS2109 022698 10/10 NOTES: 1. PDI, PDE, TCS 2. 4.00V < TERMPWR < 5.25V. 3. 0.0V < signal lines < 3.0V. 4. All signal lines = 0.0V. 5. All signal lines open. 6. Power down enabled. 7. Guaranteed by design; not production tested. 8. C14 slightly higher capacitance due to sensing circuitry. 9. Excluding PDI, PDE pins. 10. PDO output pin. 11. IBCST > 32 mA – disable termination. 12. Excluding PDE, PDI, R14, and TCS pins. 28–PIN SOIC (300 MIL) PKG 28–PIN DIM MIN MAX A IN. MM 0.094 2.39 0.105 2.67 A1 IN. MM 0.004 0.102 0.012 0.30 A2 IN. MM 0.089 2.26 0.095 2.41 b IN. MM 0.013 0.33 0.020 0.51 C IN MM 0.009 0.229 0.013 0.33 D IN. MM 0.698 17.73 0.712 18.08 e IN. MM 0.050 BSC 1.27 BSC E1 IN. MM 0.290 7.37 0.300 7.62 H IN MM 0.398 10.11 0.416 10.57 L IN MM 0.016 0.40 0.040 1.02 Θ 0 ° 8 ° |
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