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S71PL129JC0 Datasheet(PDF) 97 Page - SPANSION |
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S71PL129JC0 Datasheet(HTML) 97 Page - SPANSION |
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97 / 149 page ![]() August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 97 Advance Informatio n twc Write cycle time 70 ns tcw Chipselect to end of write 70 ns tas Address set up Time 0ns taw Address valid to end of write 70 ns tbw UB#, LB# valid to end of write 70 ns twp Write pulse width 55 ns twr Write recovery time 0ns twhz Write to output High-Z 20 ns tdw Data to write time overlap 25 ns tdh Data hold from write time 0ns tow End write to output Low-Z 5 tow Write high pulse width 7.5 ns tpc Page read cycle x tpa Page address access time x twpc Page write cycle x tcp Chip select high pulse width x Asynchronous Performance Grade -70 Density 4Mb pSRAM 3 Volt Symbol Parameter Min Max Units |
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