7

ICS950104

Advance Information

Third party brands and names are the property of their respective owners.

Byte 1: CPU, Active/Inactive Register

(1= enable, 0 = disable)

Byte 2: PCI, Active/Inactive Register

(1= enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

6

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

5

t

i

B1

41

0

M

A

R

D

S

4

t

i

B0

41

1

M

A

R

D

S

3

t

i

B9

31

2

M

A

R

D

S

2

t

i

B8

31

3

M

A

R

D

S

1

t

i

B5

31

4

M

A

R

D

S

0

t

i

B4

31

5

M

A

R

D

S

Byte 4: Reserved , Active/Inactive Register

(1= enable, 0 = disable)

Byte 5: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

6

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

5

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

4

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

3

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

2

t

i

B-

1

)

e

t

o

N

(

d

e

v

r

e

s

e

R

1

t

i

B-

1

)

e

t

o

N

(

d

e

v

r

e

s

e

R

0

t

i

B-

1

)

e

t

o

N

(

d

e

v

r

e

s

e

R

Byte 6: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

X

#

3

S

F

6

t

i

B1

11

2

F

E

R

5

t

i

B0

11

1

F

E

R

4

t

i

B4

21

z

H

M

8

4

3

t

i

B8

1

0

F

E

R

2

t

i

B

,

0

1

,

8

1

1

1

X

2

,

X

1

)

0

:

2

(

F

E

R

X

1

=

1

=

t

l

u

a

f

e

d

1

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

0

t

i

B2

,

11

0

C

/

T

K

L

C

U

P

C

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

X

)

d

e

v

r

e

s

e

R

(

6

t

i

B1

21

5

K

L

C

I

C

P

5

t

i

B0

21

4

K

L

C

I

C

P

4

t

i

B9

11

3

K

L

C

I

C

P

3

t

i

B6

11

2

K

L

C

I

C

P

2

t

i

B5

11

1

K

L

C

I

C

P

1

t

i

B4

11

0

K

L

C

I

C

P

0

t

i

B3

11

F

_

K

L

C

I

C

P

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

X

#

0

S

F

6

t

i

B-

X

#

1

S

F

5

t

i

B-

X

#

2

S

F

4

t

i

B3

31

6

M

A

R

D

S

3

t

i

B2

31

7

M

A

R

D

S

2

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

1

t

i

B5

41

K

L

C

U

P

C

0

t

i

B3

21

z

H

M

8

4

_

4

2

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

6

t

i

B-

1

z

H

M

8

4

_

4

2

z

H

M

4

2

=

1

,

z

H

M

8

4

=

0

:

t

c

e

l

e

s

5

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

4

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

3

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

2

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

1

t

i

B-

0

)

d

e

v

r

e

s

e

R

(

0

t

i

B-

0

)

d

e

v

r

e

s

e

R

(