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AD9154-EBZ Datasheet(PDF) 57 Page - Analog Devices |
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AD9154-EBZ Datasheet(HTML) 57 Page - Analog Devices |
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57 / 124 page  Data Sheet AD9154 Rev. C | Page 57 of 124 Table 56. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 10 Address Setting Description 0x453 0x00 or 0x80 Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled, Register 0x453, Bits[4:0] = 0x0: L = 1 lane per link 0x454 0x01 Register 0x454, Bits[7:0] = 0x01: F = 2 octets per frame 0x455 0x0F or 0x1F Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe 0x456 0x00 Register 0x456, Bits[7:0] = 0x00: M = 1 converter per link 0x457 0x0F Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution 0x458 0x0F or 0x2F Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample 0x459 0x20 Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per frame 0x45A 0x00 Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0 0x46C 0x01 Register 0x46C, Bits[7:0] = 0x01: Deskew Link Lane 0 to Link Lane 7 0x476 0x02 Register 0x476, Bits[7:0] = 0x02: F = 2 octets per frame 0x47D 0x01 Register 0x47D, Bits[7:0] = 0x01: Enable Link Lane 0 2 OCTETS PER LANE 16-BIT NIBBLE GROUP 1 SAMPLE PER DAC0 SERIAL JESD204B DATA (L = 1) SAMPLES SPLIT ACROSS LANES (HD = 0) NIBBLE GROUP 0 CONVERTER 0, SAMPLE 0 D15 ... D0 LANE 0, OCTET 0 LANE 1, OCTET 0 1 CONVERTER (M = 1) (F = 2) (N = 16) CONVERTER PER FRAME (S = 1) Figure 67. JESD204B Mode 10 Data Deframing |
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