AD9154-EBZ datasheet(59/124 Pages) AD

59 / 124 page

Data Sheet

AD9154

Rev. C | Page 59 of 124

To run the CGS followed by a repeated ILAS sequence test,

follow the Device Setup Guide section, but before performing

the last write (enabling the links), enable the ILAS test mode by

writing a 1 to Register 0x477, Bit 7. Then, enable the links.

When the device recognizes 4 CGS characters on each lane, it

deasserts the SYNCOUTx± signal. At this point, the transmitter

starts sending a repeated ILAS sequence.

Read Register 0x473 to verify that initial lane synchronization has

passed for all enabled link lanes. Program Register 0x300, Bit 2 = 0

to monitor the status of lanes on Link 0, and Register 0x300, Bit 2 =

1 to monitor the status of lanes on Link 1 for dual link mode.

JESD204B ERROR MONITORING

Disparity, Not in Table, and Unexpected Control

Character Errors

Per Section 7.6 of the JESD204B specification, the AD9154 can

detect disparity errors, not in table errors, and unexpected control

character errors, and can optionally issue a sync request and

reinitialize the link when errors occur.

Note that the disparity error counter counts all characters with

invalid disparity, regardless of whether they are in the 8-bit/10-bit

decoding table. This is a minor deviation from the JESD204B

specification, which only counts disparity errors when they are

in the 8-bit/10-bit decoding table.

Checking Error Counts

The error count can be checked for disparity errors, not in table

errors, and unexpected control character errors. The error counts

are on a per lane and per error type basis. Note that the lane select

and counter select are programmed into Register 0x46B and the

error count is read back from the same address. To check the

error count, complete the following steps:

1. Select the desired link lane and error type of the counter to

view. Write these to Register 0x46B according to Table 58.

To select a link lane, first select a link (Register 0x300, Bit 2

= 0 to select Link 0 or Register 0x300, Bit 2 = 1 to select

Link 1 [dual link only]). Note that, when using Link 1,

Link Lane x refers to Logical Lane x + 4.

2. Read the error count from Register 0x46B. Note the

maximum error count is equal to the error threshold set in

Table 58. Error Counters

Addr.

Bits

Variable

Description

0x46B

[6:4]

LaneSel

LaneSel = x to monitor the error

count of Link Lane x. See the notes

on link lane in Step 1 of the Checking

Error Counts section.

[1:0]

CntrSel

CntrSel = 0b00 for bad running

disparity counter.

CntrSel = 0b01 for not in table error

counter.

CntrSel = 0b10 for unexpected control

character counter.

Check for Error Count Over Threshold

In addition to reading the error count per lane and error type as

described in the Checking Error Counts section, the user can

check a register to see if the error count for a given error type

has reached a programmable threshold.

The same error threshold is used for the three error types:

disparity, not in table, and unexpected control character. The

error counters are on a per error type basis. To use this feature,

complete the following steps:

1. Program the desired error count threshold into

ERRORTHRES (Register 0x47C).

2. Read back the error status for each error type to see if the

error count has reached the error threshold.

Disparity errors are reported in Register 0x46D.

Not in table errors are reported in Register 0x46E.

Unexpected control character errors are reported in

Error Counter and IRQ Control

Write to Register 0x46D and Register 0x46F to reset or disable

the error counts and to reset the IRQ for a given lane. Note that

these are the same registers that report error count over threshold

(see the Check for Error Count Over Threshold section); thus,

the readback is not the value that was written. For each error type,

1. Select the link lane to access. To select a link lane, first

select a link (Register 0x300, Bit 2 = 0 to select Link 0,

Note that, when using Link 1, Link Lane x refers to Logical

Lane x + 4.

2. Decide whether to reset the IRQ, disable the error count,

and/or reset the error count for the given lane and error type.

3. Write the link lane and desired reset or disable action to

Table 59. Error Counter and IRQ Control: Disparity

(Register 0x46D), Not In Table (Register 0x46E), Unexpected

Control Character (Register 0x46F)

Bits

Variable

Description

RstIRQ

RstIRQ = 1 to reset IRQ for the lane

selected in Bits[2:0].

Disable_ErrCnt

Disable_ErrCnt = 1 to disable the error

count for the lane selected in Bits[2:0].

RstErrCntr

RsteErrCntr = 1 to reset the error

count for the lane selected in Bits[2:0].

[2:0]

LaneAddr

LaneAddr = x to monitor the error

count of Link Lane x. See the notes on

link lane in Step 1 of the Checking

Error Counts section.

AD9154-EBZ Datasheet(PDF) 59 Page - Analog Devices

AD9154-EBZ Datasheet(HTML) 59 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL