ML9092-01TB datasheet(45/66 Pages) OKI

45 / 66 page

FEDL9092-01

OKI Semiconductor

ML9092-01/02/03/04

45/66

Duty

Y register setting range

and loop range

Invalid address setting range

1/8

0 to 7 (00H to 07H)

1/9

0 to 8 (00H to 08H)

1/10

0 to 9 (00H to 09H)

This register is reset to “0” when the

RESET pin is made low.

• Port register A (PTA) set

—

PTA

—: don’t care

The port register A set instruction sets the output of port A.

When the PTA bit is set to “1”, a “H” level is output from the PA0 pin of general purpose port A. In the same way,

when the PTA bit is set to “0”, a “L” level is output from the PA0 pin. If the

RESET pin is pulled to a “L” level, the

PE bit (bit D2) of the control register is reset to “0”, this register is reset to “0”, and the PA0 pin goes to high

impedance.

After the reset state is released, if the PTA bit of this register is set to “1” or “0” and then the PE bit is set to “1”, the

PA0 pin is released from its high impedance state and a “H” or “L” level that corresponds to the set status of the

PTA bit, is output from the PA0 pin.

• Port register B (PTB) set

—

PTB2

PTB1

PTB0

—: don’t care

The port register B set instruction sets the output of port B. (Applies to the ML9092-01/04.)

When each bit of PTB0 to PTB2 is set to “1”, the PWM signal set in the PWM0 to PWM2 registers is output from

each of the PB0 to PB2 pins of the general purpose port B. In the same way, when each bit of PTB0 to PTB2 is set

to “0”, each of the PB0 to PB2 pins are pulled to a “L” level. If the

RESET pin is pulled to a “L” level, the PE bit

(bit D2) of the control register is reset to “0”, this register is reset to “0”, and the PB0 to PB2 pins go to high

impedance.

After the reset state is released, if the a PWM value is set in the PWM0 to PWM2 registers and then the PE bit is set

to “1”, the PB0 to PB2 registers are released from their high impedance state and a PWM waveform is output.

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