UP1817PDDA datasheet(5/21 Pages) UPI

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uP1817

uP1817-DS-F0000, Mar. 2017

www.upi-semi.com

Functional Description

VCC

EN/VBOOT

VREF1

ALERT#

SVID command

don’t care

SVID Bus

Set VID

To addr.=00h

GetReg(10h)

To addr.=00h

0.32V

VREF0

To addr.=01h

(uP1817P,IMVP8 mode)

To addr.=02h

(uP1817Q,IMVP8 mode)

To addr.=05h

(VR12.1 mode)

Set VID

GetReg(10h)

To addr.=01h

(uP1817P,IMVP8 mode)

To addr.=02h

(uP1817Q,IMVP8 mode)

To addr.=05h

(VR12.1 mode)

Figure 2. Power On Sequence with Zero Vboot

Figure 3 shows the power on sequence of non-zero Vboot

case in VR12.1/IMVP8 mode. For the non-zero Vboot case,

the reference voltage outputs (VREF0 and VREF1) starts

to ramp up to the target Vboot at the end of Ta. The slewing

time is Tb, which is also determined by the sourcing current

and timing capacitor. Then ALERT# is asserted after

internally calculated time duration Tc. For VR12.1 mode,

the ALERT# is cleared after receiving GetReg(10h) to both

address 00h and 05h. For IMVP8 mode, the ALERT# is

cleared after receiving GetReg(10h) to both addresses 00h

and 01h (for uP1817P), and addresses 00h and 02h (for

uP1817Q). Address 02h(for uP1817P) is not involved in

the ALERT# assertion/de-assertion. The ALERT# assertion

time Tc is internally determined by the amount of VID voltage

change, slew rate and operation mode.

VCC

EN/VBOOT

VREF1

ALERT#

SVID command

don’t care

SVID Bus

Set VID

To addr.=00h

GetReg(10h)

To addr.=00h

Vboot

VREF0

GetReg(10h)

To addr.=00h

GetReg(10h)

To addr.=01h

(uP1817P,IMVP8 mode)

To addr.=02h

(uP1817Q,IMVP8 mode)

To addr.=05h

(VR12.1 mode)

Figure 3.Power On Sequence with Non-zero Vboot

SVID Interface

The uP1817 adopts Intel defined SVID interface for VREFx

output voltage control. SVID is a three wire (SVCLK, SVDIO,

ALERT#) serial synchronous interface used to transfer

power management information between a microprocessor

and several VRs on the same bus, and there is an

addressing scheme for the multiple slave devices. The

SVCLK is source synchronous from the CPU, and the CPU

drives the SVCLK signal with a low voltage open drain driver.

The master may shut down the SVCLK signal to save power

when no data transfer is needed. SVDIO is a low-voltage,

open-drain data signal that master and slaves use to transfer

information to each other. The bus will operate at a typical

frequency of 25MHz. The ALERT# line is an active low signal

driven asynchronously from the slave device, indicating VR

status to the master.

VID Voltage and VREF Output Voltage

The uP1817 receives SetVID command from the processor

to determine its VREF output voltage as shown in Table 3.

The uP1817 supports 16 steps of VREF output voltage,

ranging from 0.32V to 1.52V. The controller determines the

VREF output voltage according to the VID voltage range.

VID Transition

Upon receiving valid SetVID command, the output voltage

(VREF0/1) linearly ramps up/down to the target voltage

according to VID table. The voltage transition slewing time

is determined by the operation mode (VR12.1/IMVP8),

SetVID command, the corresponding VREFx sourcing

current and the timing capacitor. The ALERT# assertion

time is determined internally.

Digital Output Current Reporting (IMON)

IMON0 and IMON1 are used to gather the output current

information and report to the processor through the SVID

bus. Connect IMON0/1 pin to a voltage source which

voltage level is proportional to each VR output current for

output current reporting. Refer to Figure 4, the uP1817

converts V

IMONX into output current information by internal

A/D converter. An internal A/D converter (ADC) converts

IMON to a digital content for output current reporting through

SVID interface. As the total load current increases, the

voltage on IMONX pin (V

IMONX) increases proportionally. As

IMONX voltage increases, the SVID register 0x15h(output

current) content increases. The 8-bit ADC input range is

typically 2.56V with 10mV/LSB, which means the SVID

IMON=2560mV. Further increase

of V

IMON (>2.56V) is allowed, but the ADC result will remain

at FFh and ALERT# remains high. The IMON reporting

function does not affect the ALERT# assertion.

IMON0

A/D

Converter

IMON1

VIMON0

VIMON1

Figure 4. Voltage Sense of Digital Output Current

Reporting (IMON)

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