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TE28F320B3BC90 Datasheet(PDF) 32 Page - Intel Corporation |
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TE28F320B3BC90 Datasheet(HTML) 32 Page - Intel Corporation |
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32 / 58 page ![]() 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 26 3UHOLPLQDU\ AC Characteristics, Continued NOTES: 1. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV. 2. Sampled, but not 100% tested. See Figure 7 for the AC waveform for read operations. See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum allowable input slew rate. # Sym Parameter Density 64 Mbit Unit Product 90 ns 100 ns VCC 2.7 V–3.6 V 2.7 V–3.6 V Note Min Max Min Max R1 tAVAV Read Cycle Time 90 100 ns R2 tAVQV Address to Output Delay 90 100 ns R3 tELQV CE# to Output Delay 1 90 100 ns R4 tGLQV OE# to Output Delay 1 20 20 ns R5 tPHQV RP# to Output Delay 150 150 ns R6 tELQX CE# to Output in Low Z 2 0 0 ns R7 tGLQX OE# to Output in Low Z 2 0 0 ns R8 tEHQZ CE# to Output in High Z 2 20 20 ns R9 tGHQZ OE# to Output in High Z 2 20 20 ns R10 tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 20 0 ns Figure 7. AC Waveform: Read Operations High Z Valid Output Address Stable Data Valid Device Address Selection Standby ADDRESSES (A) V IH V IL V IH V IL CE# (E) V IH V IL V OH V OL V IH V IL OE# (G) WE# (W) DATA (D/Q) RP# (P) High Z V IH V IL R1 R2 R4 R3 R5 R6 R7 R8 R9 R10 |
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