FS5908

Rev. 1.2

20/22

15.4.3

The register with complete reading data length 2 byte

Stop

by

Master

SCL

SDA

W

Ack

by

FS5908

Address

Byte

Start

by

Master

19

1

9

Pointer

Byte

Ack

by

FS5908

SCL

SDA

R

Ack

by

FS5908

Address

Byte

Repeat

Start by

Master

19

1

9

D15

Data Byte

Ack

by

Master

Data Byte

No

Ack

by

Master

D14 D13 D12 D11 D10 D9 D8

D7 D6D5 D4D3 D2D1 D0

D0

D1

D7

D2

D3

D4

D5

D6

A0

A1

A2

A3

A4

A5

A6

A0

A1

A2

A3

A4

A5

A6

15.5 Register Repeat Reading Process

15.5.1

Repeat reading process includes the following steps

(1)

Write address

(2)

Read data

When read by repeat reading process, the read register is the previous register that appointed by complete

reading, that is, the register that the pointer is setup.

15.5.2

The controlled register with repeat reading data length 1 byte

Stop by

Master

SCL

SDA

R

Ack

by

FS5908

Address

Byte

Start by

Master

19

1

9

D15

Data Byte

Ack

by

Master

Data Byte

No

Ack

by

Master

D14 D13 D12D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

19

A0

A1

A2

A3

A4

A5

A6

When read or write in I2C interface, if SDA signal is forced by FS5908 to logic low standard, it has to only

re-execute reading or writing process to release. (This situation won’t happen in normal timing. It happens only

when the data length read by the user is smaller than the actual length of the register.)

After writing to the register of the chip, it should take reading confirmation to make sure the written commands

not error.