M29DW128F datasheet(43/93 Pages) STMICROELECTRONICS

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M29DW128F

6 Command Interface

43/93

Set Non-

Volatile Modify

Protection Bit(5)

(6)

555

2AA

555

(BA)/

NVMP

(BA)/

NVMP

(BA)/

NVMP

DQ0

Verify Non-

Volatile Modify

Protection Bit

555

2AA

555

(BA)/

NVMP

(BA)/

NVMP

DQ0

Clear Non-

Volatile Modify

Protection

Bits(12)(13)(14)

555

2AA

555

NVMP

(BA)/

NVMP

(BA)/

NVMP

DQ0

Set Lock-Down

bit

555

2AA

555

Verify Lock-

Down bit(15)

555

2AA

555

DQ1

Set Lock Bit(7)

555

2AA

555

X1h

Clear Lock

Bit(7)

555

2AA

555

X0h

Verify Lock Bit

555

2AA

555

DQ0

Set Standard

Protection

Mode(5)(6)

555

2AA

555

DQ0

Verify Standard

Protection

Mode(5)

555

2AA

555

DQ0

Grey cells represent Read cycles. The other cells are Write cycles.

SA Protection Group Address, BA Any address in the Block, BKA Bank Address, SL Standard Protection Mode Lock bit

Address, PL Password Protection Mode Lock Bit Address, PW Password Data, PWA Password Address, RPW Password

Data Being Verified, NVMP Non-Volatile Modify Protection Bit Address, OW Extended Block Protection Bit Address, X Don’t

Care. All values in the table are in hexadecimal.

Addresses are described in Table 17: Protection Command Addresses.

During Unlock and Command cycles, if the lower address bits are 555h or 2AAh then the address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are Don't Care.

A Reset Command must be issued to return to the Read mode.

The 4th Bus Write cycle programs a protection bit (Extended Block Protection bit, Password Protection Mode Lock bit,

Standard Protection Mode Lock bit, and a block NVMP bit). The 5th and 6th cycles verify that the bit has been successively

programmed when DQ0=1. If DQ0=0 in the 6th cycle, the program command must be issued again and verified again. A

100µs delay is required between the 4th and the 5th cycle.

Data is latched on the rising edge of W.

The entire command sequence must be entered for each portion of the password.

The command sequence returns FFh if the Password Protection Mode locking bit is set.

10. The password is written over four consecutive cycles, at addresses [0-3]

11. A 2µs timeout is required between any two portions of the password.

12. A 10ms delay is required between the 4th and the 5th cycle.

13. A 12ms timeout is required between cycles 4 and 5.

Command

Bus Operations(1)(2)(3)(4)

1st

2nd

3rd

4th

5th

6th

7th

Add

Data

Add

Data

Add Data

Add

Data

Add

Data

Add

Data

Add

Data

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