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2. Pin Deﬁnitions

Table 2: Description of ESP32 Power-up and Reset Timing Parameters

Parameters

Description

Min.

Unit

Time between the 3.3 V rails being brought up and CHIP_PU being

activated

µs

Duration of CHIP_PU signal level < VIL_nRST (refer to its value in

Table 13 DC Characteristics) to reset the chip

µs

• In scenarios where ESP32 is powered on and off repeatedly by switching the power rails, while there is a

large capacitor on the VDD33 rail and CHIP_PU and VDD33 are connected, simply switching off the CHIP_PU

power rail and immediately switching it back on may cause an incomplete power discharge cycle and failure

to reset the chip adequately.

An additional discharge circuit may be required to accelerate the discharge of the large capacitor on rail

VDD33, which will ensure proper power-on-reset when the ESP32 is powered up again. Please find the

discharge circuit in Figure

ESP32-WROOM-32 Peripheral Schematics, in ESP32-WROOM-32 Datasheet.

• When a battery is used as the power supply for the ESP32 series of chips and modules, a supply voltage

supervisor is recommended, so that a boot failure due to low voltage is avoided. Users are recommended

to pull CHIP_PU low if the power supply for ESP32 is below 2.3 V. For the reset circuit, please refer to Figure

ESP32-WROOM-32 Peripheral Schematics, in ESP32-WROOM-32 Datasheet.

Notes on power supply:

• The operating voltage of ESP32 ranges from 2.3 V to 3.6 V. When using a single-power supply, the recom-

mended voltage of the power supply is 3.3 V, and its recommended output current is 500 mA or more.

• When VDD_SDIO 1.8 V is used as the power supply for external flash/PSRAM, a 2-kohm grounding resistor

should be added to VDD_SDIO. For the circuit design, please refer to Figure

ESP32-WROVER Schematics,

in ESP32-WROVER Datasheet.

• When the three digital power supplies are used to drive peripherals, e.g., 3.3 V flash, they should comply

with the peripherals’ specifications.

2.4 Strapping Pins

ESP32 has five strapping pins:

• MTDI

• GPIO0

• GPIO2

• MTDO

• GPIO5

Software can read the values of these five bits from register ”GPIO_STRAPPING”.

During the chip’s system reset release (power-on-reset, RTC watchdog reset and brownout reset), the latches

of the strapping pins sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip

is powered down or shut down. The strapping bits configure the device’s boot mode, the operating voltage of

VDD_SDIO and other initial system settings.

Each strapping pin is connected to its internal pull-up/pull-down during the chip reset. Consequently, if a strapping

pin is unconnected or the connected external circuit is high-impedance, the internal weak pull-up/pull-down will

determine the default input level of the strapping pins.

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