ACT88326VA datasheet(17/41 Pages) ACTIVE-SEMI

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ACT88326VA

Rev 1.0, 29-May-2018

Innovative PowerTM

www.active-semi.com

ActiveSwitcherTM is a trademark of Active-Semi.

POWER OFF State

The POWER OFF state is a PMIC “safe state” or “shut-

down” state. In this state, all the regulator outputs are

turned off. LDO1 has the option to be configured as an

“always-on” regulator so it stays on in the POWER OFF

state.

The ACT88326 enters POWER OFF at initial power on

when input power is applied to the IC and VIN is within

a valid range defined by the VIN_UV and VIN_OV

thresholds. nRESET is asserted low and all volatile and

non-volatile registers are reset to defaults. If the input

voltage drops below the VIN_UV threshold voltage, the

IC transitions from any other state to the POWER OFF

state. It is important to note a transition to POWER OFF

due to VIN_UV returns all volatile and non-volatile reg-

isters to their default states.

The ACT88326 can also enter POWER OFF from any

other state due to an nPB press that initiates the power

off sequence.

The ACT88326 momentarily enters POWER OFF dur-

ing a power cycle sequence.

The ACT88326 exits the POWER OFF state when the

I2C bit POWER OFF is cleared to 0, or the nPB pin is

pulled low for > 32ms.

POWER SEQUENCE START State

The POWER SEQUENCE START state is a transitional

state to power on the regulators. The IC is not intended

to operate in this state. When entering POWER SE-

QUENCE START from the SLEEP, DPSLP, and THER-

MAL states the IC transitions to the ACTIVE state when

all regulators are in regulation.

When entering POWER SEQUENCE START from the

POWER OFF state due to an nPB press, the IC remains

in POWER SEQUENCE START until nPB is released

AND the regulators are in regulation. If nPB is released

before the regulators are in regulation, the IC transitions

back to the POWER OFF state. If nPB is still pressed

and the regulators enter regulation and one of them has

a fault before nPB is released, the IC transitions back to

the POWER OFF state.

When entering POWER SEQUENCE START from the

POWER OFF state due to a power cycle sequence, the

IC stays in POWER SEQUENCE START for 0.5s before

exiting to the ACTIVE state.

ACTIVE State

The ACTIVE state is the normal operating state when

the input voltage is within the allowable range, all out-

puts are turned on, and no faults are present.

The ACT88326 enters the ACTIVE state from POWER

SEQUENCE START with a normal nPB startup, an I2C

startup, or a power cycle sequence.

It transitions from the THERMAL state directly to the

ACTIVE state when the die temperature drops back to

allowable limits. Note that when the outputs turn back

on during this transition, any outputs sequencing de-

pendent on VIN will turn on immediately. Any outputs

dependent on another output turn on with proper pro-

grammed delays.

SLEEP State

The SLEEP state is a low power mode for the operating

system. Each output can be programmed to be on or off

in the SLEEP state. The outputs follow their pro-

grammed sequencing delay times when turning on or

off as they enter or exit the SLEEP state. Buck1/2/3 can

be programmed to regulate to their VSET0 voltage,

VSET1 voltage, or be turned off in the SLEEP state.

LDO1/2 can be programmed to regulate to their VSET0

voltage or can be programmed to be turned off. Note

that LDO1/2 do not have a VSET1 voltage.

The IC enters SLEEP state via I2C register bit SLEEP,

I2C register bit SLEEP MODE, and a GPIO input pin.

The IC’s specific CMI determines the specific combina-

tion of these three inputs to enter SLEEP state. The I2C

bit SLEEP MODE is set at factory and cannot be

changed by the user. It controls the logical combination

of the GPIO input and the SLEEP register bit to enter

SLEEP state.

When SLEEP MODE is factory configured to 1, the log-

ical combination is an “OR” function and when SLEEP

MODE is factory configured to a 0, the logical combina-

tion is an “AND” function.

If no GPIOs are configured as a control input to enter

and exit SLEEP state then only the SLEEP register bit

controls the entry and exit of the SLEEP state.

Tables 1a and 1b shows the conditions to enter SLEEP

state. ACT88326’s I2C stays enabled in SLEEP state.

The IC exits the SLEEP state when the conditions to

enter SLEEP state are no longer present. Asserting nPB

low for > 32ms clears the SLEEP bit to 0 and the PMIC

exits SLEEP state.

ACT88326VA Datasheet(PDF) 17 Page - Active-Semi, Inc

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