ACT88326VA datasheet(30/41 Pages) ACTIVE-SEMI

30 / 41 page

ACT88326VA

Rev 1.0, 29-May-2018

Innovative PowerTM

www.active-semi.com

ActiveSwitcherTM is a trademark of Active-Semi.

Current Limit

Because LSG only connects to the external FET gate,

Load Switch does not have a current limit function. The

input to the Load Switch should come from an

ACT88326 Buck, LDO, or other current limited source.

Load Switch POK

The load switch internal Power OK, POK, signal can be

used in the sequencing of other power supplies. The

load switch POK signal goes active when the load

switch gate drive voltage at the LSG pin is greater than

VIN + 1V and VIN – VOUT < 100mV. Note that the ac-

tual load switch may or may not be fully on at this time

depending on the FET used for the load switch or any

additional filtering or delay circuitry connected to LSG.

PC board layout guidance

Proper parts placement and PCB layout are critical to

the operation of switching power supplies. Follow the

following layout guidelines when designing the

ACT88326 PCB. Refer to the Active-Semi ACT88326

Evaluation Kits for layout examples

1. Place the buck input capacitors as close as

possible to the IC. Refer to the Pin Descriptions

for each buck converter’s dedicated VINx and

PGNDx pins. Connect the input capacitors di-

rectly to the corresponding VINx and PGNDx

power ground pin on the top layer. Routing

these traces on the top layer eliminates the

need for vias.

2. Minimize the switch node trace length between

each SW_Bx pin and the inductor. Optimal

switch node routing is to run the trace between

the input capacitor’s pads. Using 0805 sized in-

put capacitors is recommended. Avoid routing

sensitive analog signals near these high fre-

quency, high dV/dt traces.

3. Place the LDO input capacitor close to the AVIN

pin. Connect the capacitor directly to AVIN and

AGND on the top layer.

4. The Buck output capacitors should be placed

by the inductor and connected directly to the in-

ductor and ground plane with short and wide

traces. The output capacitor ground should

make a short connection to the input capacitor

ground. If required, use multiple vias.

5. Each regulator’s FB_Bx should be Kelvin con-

nected to its output capacitor through the short-

est possible route, while keeping sufficient dis-

tance from switching nodes to prevent noise in-

jection. The IC regulates the output voltage to

this Kelvin connection.

6. The PGNDx and AGND ground pins must be

electrically connected together. Because the

AGND ground plane is used for analog, digital,

and LDO grounds, it does not need to be com-

pletely isolated from the rest of the PCB

grounds. However, take care to avoid routing

the buck converter switching currents through

the analog ground connections.

7. Connect the VIN_IO input capacitor to the

AGND ground pin.

8. Remember that all open drain outputs need

pull-up resistors.

9. Figure 4 shows the recommended power and

signal connections and routing from under the

IC. Refer to the ACT88326 evaluation kit for a

full, detailed routing example.

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