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ADRF5027BCCZN-R7 Datasheet(PDF) 9 Page - Analog Devices |
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ADRF5027BCCZN-R7 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 13 page ![]() Data Sheet ADRF5027 Rev. 0 | Page 9 of 13 THEORY OF OPERATION The ADRF5027 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to filter high frequency noise. All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V, and no dc blocking capacitors are required at the RF ports when the RF potential is equal to 0 V. The RF ports are internally matched to 50 Ω. Therefore, external matching networks are not required. Impedance matching on the RF transmission lines can improve insertion loss and return loss performance at high frequencies. The ADRF5027 integrates a driver to perform logic function internally and to provide the advantage of a simplified control interface. The driver features two digital control input pins, CTRL and EN. When the EN pin is logic low, the logic level applied to the CTRL pin determines which RF port is in insertion loss state and which RF port is in isolation state. The ADRF5027 supports an all off state control. When the EN pin is logic high, both the RF1 to RFC path and the RF2 to RFC path are in an isolation state, regardless of the logic state of the CTRL pin. The RF1 and RF2 ports are terminated to internal 50 Ω resistors, and the RFC port becomes open reflective (see Table 5). The ADRF5027 design is bidirectional with equal power handling capabilities. An RF input signal (RFIN) can be applied to the RFC port or the RF1 or RF2 port. The isolation path provides high loss between the unselected RFx port and the insertion loss path. The power-up sequence is as follows: 1. Power up GND. 2. Power up VDD. 3. Power up VSS. 4. Power up the digital control inputs. The relative order of the logic control inputs is not important. Powering up the digital control inputs before the VDD supply can inadvertently forward bias and damage the internal ESD protection structures. 5. Apply an RF input signal. The power-down sequence is the reverse order of the power-up sequence. Table 5. Control Voltage Truth Table Digital Control Input RF Paths EN CTRL RF1 to RFC RF2 to RFC Low Low Isolation (off) Insertion loss (on) Low High Insertion loss (on) Isolation (off) High Low Isolation (off) Isolation (off) High High Isolation (off) Isolation (off) |
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