PIC18F44800TESLASHML datasheet(140/484 Pages) MICROCHIP

140 / 484 page

PIC18F2480/2580/4480/4580

DS39637A-page 138

Preliminary

 2004 Microchip Technology Inc.

10.4

PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bidirectional port. The corre-

sponding Data Direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will make the corresponding PORTD pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

All pins on PORTD are implemented with Schmitt

Trigger input buffers. Each pin is individually con-

figurable as an input or output.

Four of the PORTD pins are multiplexed with outputs

P1A, P1B, P1C and P1D of the Enhanced CCP

module. The operation of these additional PWM output

pins is covered in greater detail in Section 16.0

“Enhanced

Capture/Compare/PWM

(ECCP)

Module”.

Four of the PORTD pins are multiplexed with the input

pins of the comparators. The operation of these input

pins is covered in greater detail in Section 20.0

“Comparator Module”.

PORTD can also be configured as an 8-bit wide micro-

processor port (Parallel Slave Port) by setting control

bit, PSPMODE (TRISE<4>). In this mode, the input

buffers are TTL. See Section 10.6 “Parallel Slave

Port” for additional information on the Parallel Slave

Port (PSP).

EXAMPLE 10-4:

INITIALIZING PORTD

Note:

PORTD is only available on PIC18F4X80

devices.

Note:

On a Power-on Reset, these pins are

configured as analog inputs.

CLRF

PORTD

; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISD

; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

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