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PIC18F44800TE/ML Datasheet(PDF) 141 Page - Microchip Technology

Part # PIC18F44800TE/ML
Description  28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
PDF  484 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F44800TE/ML Datasheet(HTML) 141 Page - Microchip Technology

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 2004 Microchip Technology Inc.
Preliminary
DS39637A-page 139
PIC18F2480/2580/4480/4580
TABLE 10-7:
PORTD I/O SUMMARY
Pin Name
Function
I/O
TRIS
Buffer
Description
RD0/PSP0/
C1IN+
RD0
OUT
0
DIG
LATD<0> data output.
IN
1
ST
PORTD<0> data input.
PSP0
OUT
x
DIG
Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled).
IN
x
TTL
Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled).
C1IN+
IN
1
ANA
Comparator 1 positive input B. Default on POR. This analog input overrides the digital
input (read as clear – low level).
RD1/PSP1/
C1IN-
RD1
OUT
0
DIG
LATD<1> data output.
IN
1
ST
PORTD<1> data input.
PSP1
OUT
x
DIG
Parallel Slave Port (PSP) data output (overrides the TRIS<1> control when enabled).
IN
x
TTL
Parallel Slave Port (PSP) data input (overrides the TRIS<1> control when enabled).
C1IN-
IN
1
ANA
Comparator 1 negative input. Default on POR. This analog input overrides the digital
input (read as clear – low level).
RD2/PSP2/
C2IN+
RD2
OUT
0
DIG
LATD<2> data output.
IN
1
ST
PORTD<2> data input.
PSP2
OUT
x
DIG
Parallel Slave Port (PSP) data output (overrides the TRIS<2> control when enabled).
IN
x
TTL
Parallel Slave Port (PSP) data input (overrides the TRIS<2> control when enabled).
C2IN+
IN
1
ANA
Comparator 2 positive input. Default on POR. This analog input overrides the digital
input (read as clear – low level).
RD3/PSP3/
C2IN-
RD3
OUT
0
DIG
LATD<3> data output.
IN
1
ST
PORTD<3> data input.
PSP3
OUT
x
DIG
Parallel Slave Port (PSP) data output (overrides the TRIS<3> control when enabled).
IN
x
TTL
Parallel Slave Port (PSP) data input (overrides the TRIS<3> control when enabled).
C2IN-
IN
1
ANA
Comparator 2 negative input. Default input on POR. This analog input overrides the
digital input (read as clear – low level).
RD4/PSP4/
ECCP1/P1A
RD4
OUT
0
DIG
LATD<4> data output.
IN
1
ST
PORTD<4> data input.
PSP4
OUT
x
DIG
Parallel Slave Port (PSP) data output (overrides the TRIS<4> control when enabled).
IN
x
TTL
Parallel Slave Port (PSP) data input (overrides the TRIS<4> control when enabled).
ECCP1
OUT
0
DIG
ECCP1 compare output.
IN
1
ST
ECCP1 capture input.
P1A
OUT
0
DIG
ECCP1 Enhanced PWM output, channel A.
RD5/PSP5/
P1B
RD5
OUT
0
DIG
LATD<5> data output.
IN
1
ST
PORTD<5> data input.
PSP5
OUT
X
DIG
Parallel Slave Port (PSP) data output (overrides the TRIS<5> control when enabled).
IN
x
TTL
Parallel Slave Port (PSP) data input (overrides the TRIS<5> control when enabled).
P1B
OUT
0
DIG
ECCP1 Enhanced PWM output, channel B.
RD6/PSP6/
P1C
RD6
OUT
0
DIG
LATD<6> data output.
IN
1
ST
PORTD<6> data input.
PSP6
OUT
x
DIG
Parallel Slave Port (PSP) data output (overrides the TRIS<6> control when enabled).
IN
x
TTL
Parallel Slave Port (PSP) data input (overrides the TRIS<6> control when enabled).
P1C
OUT
0
DIG
ECCP1 Enhanced PWM output, channel C.
RD7/PSP7/
P1D
RD7
OUT
0
DIG
LATD<7> data output.
IN
1
ST
PORTD<7> data input.
PSP7
OUT
x
DIG
Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled).
IN
x
TTL
Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled).
P1D
OUT
0
DIG
ECCP1 Enhanced PWM output, channel D.
Legend:
PWR = Power Supply, OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input



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