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CY28317-2
Document #: 38-07094 Rev. *B
Page 9 of 21
Bit 5
Reserved
0
Reserved
Bit 4
RST_EN_WD
0
This bit will enable the generation of a Reset pulse when a Watchdog Timer
time-out occurs.
0 = Disabled
1 = Enabled
Bit 3
RST_EN_FC
0
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
Bit 2
WD_TO_STATU
S
0
Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write)
Bit 1
WD_EN
0
0 = Stop and reload Watchdog Timer. Unlock CY28317-2 from recovery
frequency mode.
1 = Enable Watchdog Timer. It will start counting down after a frequency
change occurs.
Note: CY28317-2 will generate a system reset, reload a recovery frequency,
and lock itself into a recovery frequency mode after a Watchdog Timer time-
out occurs. Under recovery frequency mode, CY28317-2 will not respond to
any attempt to change output frequency via the SMBus control bytes. System
software can unlock CY28317-2 from its recovery frequency mode by clearing
the WD_EN bit.
Bit 0
CPU0:1_DRV
0
CPU0:1 clock output drive strength
0 = Normal
1 = High Drive
Byte 9: System RESET and Watchdog Timer Register (continued)
Bit
Name
Default
Pin Description
Byte 10: Skew Control Register
Bit
Name
Default
Description
Bit 7
CPU0:1_Skew2
0
CPU 0:1 output skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 6
CPU0:1_Skew1
0
Bit 5
CPU0:1_Skew0
0
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
CPUT&C_Skew1
0
CPUT and CPUC output skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Bit 0
CPUT&C_Skew0
0
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