CY28317PVC-2 datasheet(1/21 Pages) CYPRESS

Part #	CY28317PVC-2

Description	FTG for Mobile VIA PL133T and PLE133T Chipsets

PDF	21 Pages

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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FTG for Mobile VIA™ PL133T and PLE133T Chipsets

CY28317-2

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07094 Rev. *B

Revised December 26, 2002

17-2

Features

• Single-chip system frequency synthesizer for mobile

VIA PL133T and PLE133T chipsets

• Programmable clock output frequency with less than

1 MHz increment

• Integrated fail-safe Watchdog Timer for system

recovery

• Automatic switch to HW-selected or SW-programmed

clock frequency when Watchdog Timer time-out occurs

• System RESET generation capability after a Watchdog

Timer time-out occurs or a change in output frequency

via SMBus interface

• Support SMBus byte Read/Write and block Read/ Write

operations to simplify system BIOS development

• Vendor ID and Revision ID support

• Programmable drive strength for SDRAM and PCI

output clocks

• Programmable output skew for CPU, PCI and SDRAM

• Maximized EMI Suppression using Cypress’s Spread

Spectrum technology

• Available in 48-pin SSOP and TSSOP packages

Key Specifications

CPU to CPU Output Skew:.......................................... 175 ps

PCI to PCI Output Skew: ............................................. 500 ps

Block Diagram

Pin Configuration

Note:

1.

Signals marked with ‘*’ have internal pull-up resistors.

[1]

VDD_REF

REF0

PCI0_F/FS4*

XTAL

PLL Ref Freq

PLL 1

X2

X1

REF1/FS2*

VDD_PCI

PCI2:6

48MHz/FS0*

24_48MHz/FS1*

PLL2

÷2,3,4

OSC

VTT_PWRGD#

VDD_48MHz

SMBus

SDATA

Logic

SCLK

SDRAM0:6

SDRAMIN

7

VDD_SDRAM

PCI1/FS3*

CPU0:1, CPUT, CPUC

÷2

GND_CPU

*FS2/REF1

REF0

VTT_PWRGD#

VDD_REF

GND_REF

X1

X2

VDD_PCI

*FS4/PCI0_F

*FS3/PCI1

GND_PCI

PCI2

PCI3

PCI4

PCI5

PCI6

SDRAMIN

*CPU_STOP#

*PCI_STOP#

*PD#

*MULT_SEL

GND_48MHz

SDATA

CPU0

CPU1

VDD_CPU_2.5

VDD_CPU_3.3

CPUT

CPUC

GND_CPU

RST#

IREF

SDRAM6

GND_SDRAM

SDRAM0

SDRAM1

VDD_SDRAM

SDRAM2

SDRAM3

GND_SDRAM

SDRAM4

SDRAM5

VDD_SDRAM

VDD_48MHz

48MHz/FS0*

24_48MHz/FS1*

SCLK

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Logic

Reset

RST#

IREF

MULT_SEL

PCI_STOP#

CPU_STOP#

PD#

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