Low Voltage CMOS Logic – 74LVC1G125

 

 

Single Non-Inverting Buffer/Line Driver with 3-State Output in bare die form

Rev 1.0

29/06/19

Features:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Inputs directly interface TTL

The 74LVC1G125 is a single non-inverting buffer/line

driver with 3-state output. The 3-state output is

controlled by the output enable input (OE). A HIGH-level

at pin OE sets the output to a high-impedance OFF-

state. The device is driven by 3.3V or 5V inputs enabling

use of this device in a mixed voltage environment. The

part operates over a 1.65V to 5.5V supply range and is

fully specified for partial power-down applications using

damaging backflow current through the device at power

down. The device suits level translation and interfacing

TTL to CMOS logic.

Inputs accept up to 5.5V enabling level translation

Low Quiescent Current: 4µA max

Tiny die size.

Ordering Information

 

Description

Die Dimensions in µm (mils)

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

590 (23)

For High Reliability versions of this product please see

54LVC1G125

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 280µm(11 Mils) – On request

590 x 480

µm

Die Size (Unsawn)

23 x 19

mils

Minimum Bond Pad Size

70 x 70

2.76 x 2.76

µm

mils

Die Thickness

280 (±20)

µm

11.02 (±0.79)

mils

Top Metal Composition

Al-Si-Cu 3 µm

Back Metal Composition

N/A – Bare Si

Assembled into Ceramic Package – On request

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