LXT975B datasheet(16/74 Pages) INTEL

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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers

Datasheet

Table 8.

LXT974 and LXT975 Hardware Control Interface Signal Descriptions

Pin#

Symbol

Type1

Signal Description2

116

CFG_0

(Global)

Configuration Control 0.

When A/N is enabled, Low to High transition on CFG_0 causes auto-negotiate to restart on

all ports and 0.9 = 1.

When A/N is disabled, this input selects operating speed and directly affects bit 0.13.

When CFG_0 is High, 100 Mbps is selected and bit 0.13 = 1.

When CFG_0 is Low, 10 Mbps is selected and bit 0.13 = 0.

115

CFG_1

(Global)

Configuration Control 1.

When A/N is enabled, CFG_1 determines operating speed advertisement capabilities in

combination with CFG_2 and FDE on all ports. See Table 16 on page 26 for details.

When A/N is disabled, CFG_1 enables 10 Mbps link test and directly affects bit 19.8.

When CFG_1 is High, 10 Mbps link test is disabled and bit 19.8 = 1.

When CFG_1 is Low, 10 Mbps link test is enabled and bit 19.8 = 0.

114

CFG_2

(Global)

Configuration Control 2.

When A/N is enabled, CFG_2 determines operating speed advertisement capabilities in

combination with CFG_1 on all ports. See Table 16 on page 26 for details.

When A/N is disabled, this input selects either TP or FX interface. When FX interface is

selected, the LXT974/975 automatically disables the scrambler. For correct FX operation,

100 Mbps operation must also be selected.

Note: It is recommended to set the network interface for each port independently, via the SD/

TPn pins. See Table 1 and Table 4 for Signal Detect / TP Select signal descriptions and

operation.

When CFG_2 is Low, TP is enabled and bit 19.2 = 0.

When CFG_2 is High, FX is enabled and bit 19.2 = 1.

110

FDE

(Global)

Full-Duplex Enable - All Ports.

When High, enables full-duplex operation on all ports.

117

FDE_FX

Full-Duplex Enable - FX Ports only.

When High, enables full-duplex operation on all ports set for FX mode operation. This pin is

ignored on ports set for TP mode.

113

BYPSCR

(Global)

Bypass Scrambler.

In TP mode, enables or bypasses Scrambler operation and directly affects MDIO

When High, Scrambler is bypassed and bit 19.3 = 1.

When Low, Scrambler is enabled and bit 19.3 = 0.

In FX mode, the LXT974/975_ automatically bypasses the Scrambler. This pin has no

effect selecting Scrambler bypass.

111

AUTOENA

(Global)

Auto-Negotiation Enable. When High, enables auto-negotiation on all ports.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain.

2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).

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