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LXT975B Datasheet(PDF) 31 Page - Intel Corporation

Part # LXT975B
Description  Fast Ethernet 10/100 Quad Transceivers
PDF  74 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

LXT975B Datasheet(HTML) 31 Page - Intel Corporation

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Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Datasheet
31
In 100FX mode, the LXT974/975 transmits and receives NRZI signals across the PECL interface.
An external 100FX transceiver module is required to complete the fiber connection.
As shown in Figure 14, the MAC starts each transmission with a preamble pattern. As soon as the
LXT974/975 detects the start of preamble, it transmits a J/K symbol (Start of Stream Delimiter,
SSD) to the network. It then encodes and transmits the rest of the packet, including the balance of
the preamble, the Start of Frame Delimiter (SFD), packet data, and CRC. Once the packet ends,
the LXT974/975 transmits the T/R symbol End-of-Stream Delimiter (ESD) and then returns to
transmitting Idle symbols.
Figure 13. 100BASE-TX Data Flow
Figure 14. 100BASE-TX Frame Structure
1. Four independent MII ports serve four independent Network ports. Network port configurations are independently
selectable. MII port speed is set to match the associated Network port.
2. The Scrambler can be bypassed by setting 19.3 = 1.
D0
D1
D2
D3
Parallel
to
Serial
Serial
to
Parallel
D0
D1
D2
D3
4B/5B
5B/4B
S0
S1
S2
S3
S4
MLT3
0
+1
-1
00
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
Scramble
De-
Scramble
Standard MII Mode Data Flow
P0
P1
P6
SFD
64-Bit Preamble
(8 Octets)
Start of Frame
Delimiter (SFD)
DA
DA
SA
SA
Destination and Source
Address (6 Octets each)
L1
L2
Packet Length
(2 Octets)
D0
D1
Dn
Data Field
(Pad to minimum packet size)
Frame Check Field
(4 Octets)
CRC
I0
InterFrame Gap / Idle Code
(> 12 Octets)
Replaced by
/T/R/ code-groups
End of Stream Delimiter (ESD)
IFG
Replaced by
/J/K/ code-groups
Start of Stream
Delimiter (SSD)



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