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LXT975B Datasheet(PDF) 62 Page - Intel Corporation |
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LXT975B Datasheet(HTML) 62 Page - Intel Corporation |
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62 / 74 page ![]() LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 62 Datasheet Figure 38. Power Down Timing Table 41. Power Down Timing Parameters Parameter Sym Min Typ 1 Max Units Power Down recovery time tPDR – 50 – ms 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. Figure 39. Serial LED Timing Table 42. Serial LED Timing Parameters Parameter Symbol Min Typ 1 Max Units LEDENA setup to LEDCLK falling edge tena1 5 12 – ns LEDENA hold from LEDCLK falling edge tena2 15 21 – ns LEDDAT setup to LEDCLK falling edge tdat1 5 12 – ns LEDDAT hold from LEDCLK falling edge tdat2 15 21 – ns 1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing. tPDR VCC RESET MDIO,etc VCC = 4.75V tena1 LEDENA LEDCLK LEDDAT tena2 tdat1 tdat2 |
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