STA450A datasheet(8/66 Pages) STMICROELECTRONICS

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STA450A

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Figure 5. STA450A Clocks Generation System

The system clock

The system clock sent to the DSP core and the peripherals can be derived from 4 sources of clock and the se-

lection is performed by m4. The control of m4 is performed by the 2 input pins (CLK_M1 & CLK_M0):

– 00 sys_clk = CLK_IN

– 01 sys_clk = CLK_IN divided by 2

– 10 sys_clk = sys_clockout

– 11sys_clk = sys_clockout divided by 2

In the chip, the duty cycle of the internal system clock must be as close as possible 50%.

When the sys_clk is derived from the external clock source (CLK_IN), the divider by 2 can be used to ensure a

50% duty cycle.

When the sys_clk is derived from the system PLL, the duty cycle of the sys_clockout signal is 50%. The divider

by 2 can be used to slow down the clock at a lower frequency than the minimum that can achieve the System

PLL.

The CLK_OUT pad is driven by the sys_clk divided by a programmable division factor ranging from 1 to 16; the

sys_clk frequency is divided by 2 * (N+1), where N is the value programmed with register sys_paddiv [3:0].

Configuration Equations for the System PLL:

X = pllsys_Xmodulo

MMDSP +

CORE

PCM INTERFACE

USSIO0

sysclk

USSIO1

USSIO2

USSIO3

internal_pcmclk

MMIO

PERIPHERALS

DIV

MD+1

PFD

FREF

FIN

PLL DISABLE

/ 2

VCO

DIV

MD+1

DIV

MD+1

SWITCHING

CIRCUIT

CHARGE

PUMP

SYSTEM PLL

sys_paddiv(3:0)

sys_clockout

/ 2

(N+1)

OCLK

CLK_IN

CLKOUT

Emulation Unit

RS232 Interfaces

Host Interface

Timers Ext Interrupt

GPIO

I2C master

IO ROM

IT remap

FRAC0

sys_clk

DIV

MD+1

PFD

FREF

FIN

PLL DISABLE

VCO

DIV

MD+1

DIV

MD+1

audio sample counter

SWITCHING

CIRCUIT

CHARGE

PUMP

AUDIO PLL

audio_clockout

external filter

FRAC0

D02AU1415

out

-------------

Fref

-----------------

reference

65536

-----------------------------





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