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TLV9062IDDFR Datasheet(PDF) 22 Page - Texas Instruments |
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TLV9062IDDFR Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 79 page ![]() ±100 ±75 ±50 ±25 0 25 50 75 100 0 0.3 0.6 0.9 Settling time (µs) C032 -150 -125 -100 -75 -50 -25 0 25 50 75 100 0 0.3 0.6 0.9 1.2 1.5 Settling time (µs) C033 0 15 30 45 60 75 90 0 10 20 30 40 50 60 70 80 90 100 Capacitive Load (pF) C037 0 40 80 120 160 200 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Output Voltage (V) C023 0 20 40 60 80 100 120 140 10M 100M 1G Frequency (Hz) C041 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 100 1k 10k 100k 1M 10M Frequency (Hz) C038 22 TLV9061, TLV9062, TLV9064 SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: TLV9061 TLV9062 TLV9064 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated Typical Characteristics (continued) at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) PRF = –10 dBm Figure 31. Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency V+ = 2.75 V V– = –2.75 V Figure 32. Channel Separation vs Frequency VS = 5.5 V Figure 33. Phase Margin vs Capacitive Load VS = 5.5 V Figure 34. Open Loop Voltage Gain vs Output Voltage Figure 35. Large Signal Settling Time (Positive) Figure 36. Large Signal Settling Time (Negative) |
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