TLV9062IDDFR datasheet(29/79 Pages) TI1

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TLV9061, TLV9062, TLV9064

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SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019

Product Folder Links: TLV9061 TLV9062 TLV9064

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12 Layout

12.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp

itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources

local to the analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply

applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care

to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more

detailed information, see Circuit Board Layout Techniques.

•

In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much

better as opposed to running the traces in parallel with the noisy trace.

•

Place the external components as close to the device as possible. As illustrated in Figure 42, keeping RF and

RG close to the inverting input minimizes parasitic capacitance on the inverting input.

•

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

•

Cleaning the PCB following board assembly is recommended for best performance.

•

Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to

remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-

cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

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