EM78P258NN datasheet(21/81 Pages) EMC

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EM78P258N

8-Bit Microprocessor with OTP ROM

Product Specification (V1.0) 06.16.2005

• 15

(This specification is subject to change without further notice)

6.2

Special Purpose Registers

6.2.1 A (Accumulator)

Internal data transfer, or instruction operand holding. It cannot be addressed.

6.2.2 CONT (Control Register)

INTE

INT

PSTE

PST2

PST1

PST0

NOTE

■ The CONT register is both readable and writable.

■ Bit 6 is read only.

Bit 7 (INTE): INT signal edge

0 = interrupt occurs at the rising edge on the INT pin

1 = interrupt occurs at the falling edge on the INT pin

Bit 6 (INT):

Interrupt enable flag

0 = masked by DISI or hardware interrupt

1 = enabled by the ENI/RETI instructions

This bit is readable only.

Bit 5 (TS):

TCC signal source

0 = internal instruction cycle clock. P54 is bi-directional I/O pin.

1 = transition on the TCC pin

Bit 4 (TE):

TCC signal edge

0 = increment if the transition from low to high takes place on the TCC

1 = increment if the transition from high to low takes place on the TCC

pin.

Bit 3 (PSTE): Prescaler enable bit for TCC

0 = prescaler disable bit. TCC rate is 1:1.

1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.

Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits

PST2

PST1

PST0

TCC Rate

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

EM78P258NN Datasheet(PDF) 21 Page - ELAN Microelectronics Corp

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