EM78P258NN datasheet(45/81 Pages) EMC

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EM78P258N

8-Bit Microprocessor with OTP ROM

Product Specification (V1.0) 06.16.2005

• 39

(This specification is subject to change without further notice)

6.5.2 The T and P Status under STATUS (R3) Register

A RESET condition is initiated by one of the following events:

1. Power-on reset

2. /RESET pin input "low"

3. WDT time-out (if enabled).

The values of RST, T, and P as listed in the table below, are used to check how the

processor wakes up.

Reset Type

RST

Power-on

/RESET during Operating mode

/RESET wake-up during SLEEP mode

WDT during Operating mode

WDT wake-up during SLEEP mode

Wake-up on pin change during SLEEP mode

*P: Previous status before reset

The following shows the events that may affect the status of T and P.

Event

RST

Power-on

WDTC instruction

WDT time-out

SLEP instruction

Wake-up on pin changed during SLEEP mode

*P: Previous value before reset

6.6

Interrupt

The EM78P258N has five interrupts as listed below:

1. TCC, TCCA, TCCB, TCCC overflow interrupt

2. Port 5 Input Status Change Interrupt

3. External interrupt [(P60, /INT) pin]

4. Analog to Digital conversion completed

5. IR/PWM underflow interrupt

Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV

R5,R5") is necessary. Each Port 5 pin will have this feature if its status changes. The

Port 5 Input Status Change Interrupt will wake-up the EM78P258N from the sleep

mode if it is enabled prior to going into the sleep mode by executing SLEP instruction.

When wake-up occurs, the controller will continue to execute program in-line if the

global interrupt is disabled. If enabled, the global interrupt will branch out to the

interrupt vector 006H.

EM78P258NN Datasheet(PDF) 45 Page - ELAN Microelectronics Corp

EM78P258NN Datasheet(HTML) 45 Page - ELAN Microelectronics Corp

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