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SAFC161PI Datasheet(PDF) 62 Page - Infineon Technologies AG |
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SAFC161PI Datasheet(HTML) 62 Page - Infineon Technologies AG |
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62 / 400 page  &3, 7KH &HQWUDO 3URFHVVLQJ 8QLW &38 User’s Manual 4-14 1999-08 The System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset (see hardware effectable bits). SYSCON System Control Register SFR (FF12 H/89H) Reset value: 0XX0 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STKSZ ROM S1 SGT DIS ROM EN BYT DIS CLK EN WR CFG CS CFG - OWD DIS BD RST EN XPEN VISI- BLE XPER SHA- RE rw rw rw rwh rwh rw rwh rw - rwh rw rw rw rw Bit Function XPER-SHARE XBUS Peripheral Share Mode Control 0: External accesses to XBUS peripherals are disabled 1: XBUS peripherals are accessible via the ext. bus during hold mode VISIBLE Visible Mode Control 0: Accesses to XBUS peripherals are done internally 1: XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0: Accesses to the on-chip X-Peripherals and their functions are disabled 1: The on-chip X-Peripherals are enabled and can be accessed BDRSTEN Bidirectional Reset Enable Bit 0: Pin RSTIN is an input only. 1: Pin RSTIN is pulled low during the internal reset sequence after any reset. OWDDIS Oscillator Watchdog Disable Bit 0: The on-chip oscillator watchdog is enabled and active. 1: The on-chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator input. CSCFG Chip Select Configuration Control 0: Latched CS mode. The CS signals are latched internally and driven to the (enabled) port pins synchronously. 1: Unlatched CS mode. The CS signals are directly derived from the address and driven to the (enabled) port pins. WRCFG Write Configuration Control (Set according to pin P0H.0 during reset) 0: Pins WR and BHE retain their normal function 1: Pin WR acts as WRL, pin BHE acts as WRH |
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