DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
2
Final
Version: DM9601-DS-F01
June 22, 2002
Table of Contents
1. General Description ..............................................1
2. Block Diagram……………………………………… 1
3. Features ................................................................4
3.1 USB Characteristics............................................4
3.2 Tansceiver ..........................................................4
3.3 Other ...................................................................4
4. Pin Configuration ..................................................5
5. Pin Description......................................................6
5.1 MII Interface ........................................................6
5.2 EEPROM Interface .............................................6
5.3 USB Interface.......................................................... 6
5.4 Clock Interface ....................................................7
5.5 LED Interface ......................................................7
5.6 10/100 PHY/Fiber ...............................................7
5.7 Miscellaneous Pins .............................................7
5.8 Power Pins..........................................................8
6. USB Standard Command .....................................9
6.1 Supported Standard Command ..........................9
6.2 Not Support Standard Commend .......................9
7. Vendor Command....................................................10
7.1 Register Type....................................................10
7.2 Memory Type ....................................................11
8. Interface 0 Configuration.....................................12
8.1 Endpoint 1.........................................................12
8.2 Endpoint 2.........................................................12
8.3 Endpoint 3.........................................................12
9. Descriptor Values................................................13
9.1 Device Descriptor/18-Byte ................................13
9.2 Configuration0 Descriptor/8-Byte ........................14
9.3 Interface0 Descriptor/9-Byte .............................14
9.4 Endpoint1 Descriptor/6-Byte.............................15
9.5 Endpoint3 Descriptor/6-Byte.............................16
9.6 String0 Descriptor/Code array ..........................16
9.7 Descriptor of string1/2/3 are loaded from
EEPROM .........................................................17
10. Vendor Control and Status Register Set...........18
10.1 Network Control Register (00H)......................19
10.2 Network Status Register (01H) .......................19
10.3 TX Control Register (02H) ..............................20
10.4 TX Status Register I (03H)..............................20
10.5 TX Status Register II (04H).............................21
10.6 RX Control Register (05H) ..............................21
10.7 RX Status Register (06H) ...............................21
10.8 Receive Overflow Counter Register (07H) .....22
10.9 Back Pressure Threshold Register (08H) .......22
10.10 Flow Control Threshold Register (09H) ........22
10.11 RX/TX Flow Control Register (0AH) .............22
10.12 EEPROM & PHY Control Register (0BH) .....23
10.13 EEPROM & PHY Address Register (0CH) ...23
10.14 EEPROM & PHY Data
Register(EE_PHY_L:0DH EE_PHY_H:0EH) ..23
10.15 Wake Up Control Register (0FH)..................24
10.16 Physical Address Register (10H~15H) .........24
10.17 Multicast Address Register (16H~1DH)........24
10.18 General Purpose Control Register
(1EH)……….………………………………….….24
10.19 General Purpose Register (1FH) ..................25
10.20 TX SRAM Write Pointer Address Register
(20H~21H) .......................................................25
10.21 TX SRAM read Pointer Address Register
(22H~23H) .......................................................25
10.22 RX SRAM Write Pointer Address Register
(24H~25H) .......................................................25
10.23 RX SRAM Write Pointer Address Register
(26H~27H) .......................................................25
10.24 Vendor ID Register (28H~29H).....................26
10.25 Product ID Register (2AH~2BH) ...................26
10.26 Chip Revision Register (2CH).......................26
10.27 USB Device Address Register (F0H)............26
10.28 Receive Packet Counter Register (F1H) ......26
10.29 Transmit Packet Counter/USB Status Register
(F2H)................................................................26
10.30 USB Control Register (F4H) ........................27
10.31 EEPROM Format ……………………………..27
11. MII Register Description....................................28
11.1 Basic Mode Control Register (BMCR) – 00 ....29
11.2 Basic Mode Status Register (BMSR) – 01......30
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