CS7620 datasheet(50/70 Pages) CIRRUS

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CS7620

DS301PP2

4.32

Horizontal Timing Control - H3

Default = 4Ch; Read/Write (address 2Bh)

Bit Number

765432

Bit Name

Reserved

h3d

h3f_reg2

h3f_reg1

h3f_reg0

h3f_reg2

h3f_reg1

h3f_reg0

Default

1001100

Bit

Mnemonic

Function

Reserved

6h3d

H3 Default Setting: During the vertical shift time, the horizontal clocks are

held in one state. This bit controls whether H3 is held high or low during this

time.

A “0” indicates that the signal state is low, a “1” indicates that the signal state

is high.

h3f_reg2

H3 Falling Edge:The phase of the falling edge of H3 can be programmed

through this register. The falling edge of H3 corresponds to the rising edge of

the internally selected clock. The phases of these clocks are shown in Figure

19, with the complemented clocks being the inverse of these.

0 = t0

1 = t1

2 = t2

3 = t3

4 = t4

5 = t5

6 = t6

7 = t7

(See Figure 19)

h3f_reg1

h3f_reg0

h3f_reg2

H3 Rising Edge:The phase of the rising edge of H3 can be programmed

through this register. The rising edge of H3 corresponds to the rising edge of

the internally selected clock. The phases of these clocks are shown in Figure

19, with the complemented clocks being the inverse of these.

0 = t0

1 = t1

2 = t2

3 = t3

4 = t4

5 = t5

6 = t6

7 = t7

(See Figure 19)

h3f_reg1

h3f_reg0

CS7620 Datasheet(PDF) 50 Page - Cirrus Logic

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