Advanced Clock Drivers Devices

12

Freescale Semiconductor

MPC92433

Read Mode (R/W = 1)

The configuration registers are read by the bus controller

by the initiation of a read transfer. The MPC92433 supports

read transfers immediately after the first byte without a

change in the transfer direction. Immediately after the bus

controller sends the slave address, the MPC92433

acknowledges and then sends both configuration register

PLL_L and PLL_H (back-to-back) to the bus controller. The

CMD register cannot be read. In order to read the two

synthesizer registers and the current PLL configuration

setting, the user can 1) read PLL_L, PLL_H, write the GET

command (loads the current configuration into PLL_L,

PLL_H) and read PLL_L, PLL_H again. Note that the PLL_L,

PLL_H registers and divider settings may not be equivalent

after the following cases:

a.

Writing the INC command

b.

Writing the DEC command

c.

Writing PLL_L, PLL_H registers with a new

configuration and not writing the LOAD command.

Device Startup

General Device Configuration

It is recommended to reset the MPC92433 during or

immediately after the system powers up (MR = 0). The device

acquires an initial PLL divider configuration through the

indicated by an assertion of the LOCK signal which

completes the startup procedure. It is recommended to

disable the outputs (CLK_STOPx = 0) until PLL lock is

achieved to suppress output frequency transitions. The

output frequency can be reconfigured at any time through

either the parallel or the serial interface.

Note that a PLL configuration obtained by the parallel

programming mode (parallel or serial). Refer to the I2C —

Register Access in Parallel Mode section for additional

information on how to read a PLL startup configuration

Starting-Up Using the Parallel Interface

The simplest way to use the MPC92433 is through the

parallel interface. The serial interface pins (SDA, SDL) and

ADDR[1:0]) can be left open and PLOAD is set to logic low.

After the release of MR and at any other time the PLL/output

frequency configuration is directly set to through the M[9:0],

NA[2:0], NB, and P pins.

Set PLOAD = 1, CLK_STOPx = L and leave the parallel

interface pins (M[9:0], NA[2:0], N, and P) open. The PLL

dividers are configured by the default configuration at the low-

to-high transition of MR. This initial PLL configuration can be

re-programmed to the final VCO frequency at any time

through the serial interface. After the PLL achieved lock at the

desired VCO frequency, enable the outputs by setting

CLK_STOPx = H. PLL lock and re-lock (after any

configuration change through M or P) is indicated by LOCK

being asserted.

Table 19. Configuration Register Read Transfer

1 bit

7 bits

1 bit

1 bit

8 bits

1 bit

8 bits

1 bit

1 bit

Start

Slave address

R/W

ACK

PLL_L

ACK

PLL_H

ACK

Stop

1. xx = state of ADR1, ADR0 pins

1

Data

Data

Master

Master

Mast

Slave

Slave

Mast

Slave

Master

Slave

1. The parallel interface pins M[9:0], NA[2:0], N, and P may be left open (floating). In this case the initial PLL configuration will have the default

of 250 MHz.

2. The initial PLL configuration is independent on the selected programming mode (PLOAD low or high)

MR

P, M, N

PLOAD

LOCK

CLK_STOPx

QA, QB

Stable & Valid

Acquiring Lock

PLL Lock

Disabled (Low)

Active