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PR533 Datasheet(PDF) 20 Page - NXP Semiconductors |
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PR533 Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 36 page ![]() PR533_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.6 — 27 October 2014 206436 20 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution 10.12 Input pin characteristics for SCL [1] To minimize power consumption when in soft power-down mode, the limit is VDDD 0.4 V. [2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V. [3] The PR533 has a slope control according to the I2C-bus specification for the Fast mode. The slope control is always present and not dependent of the I2C-bus speed. 10.13 Input/output pin characteristics for SDA [1] To minimize power consumption when in soft power-down mode, the limit is VDDD 0.4 V. [2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V. [3] The PR533 has a slope control according to the I2C-bus specification for the Fast mode. The slope control is always present and not dependent of the I2C-bus speed. Table 23. Input/output drain output pin characteristics for SCL I2C interface Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage [1] 0.7 V DD(PVDD) -VDDD V VIL LOW-level input voltage [2] 0- 0.3 V DDD V VOL LOW-level output voltage VDDD =3V; IOL = 4mA 0- 0.3 V IIH HIGH-level input current VI =VDDD 1- 1 A IIL LOW-level input current VI =0V 1- 1 A ILI input leakage current RSTPD_N = 0.4 V 1- 1 A Ci input capacitance - 2.5 pF CL load capacitance - - 30 pF tr rise time of both SDA and SCL signals [3] 20 - 300 ns tf fall time of both SDA and SCL signals [3] 20 - 300 ns Table 24. Input/output drain output pin characteristics for SDA I2C interface Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage [1] 0.7 V DD(PVDD) -VDDD V VIL LOW-level input voltage [2] 0- 0.3 V DDD V VOL LOW-level output voltage VDDD =3V; IOL = 4mA 0- 0.3 V IIH HIGH-level input current VI =VDDD 1- 1 A IIL LOW-level input current VI =0V 1- 1 A ILI input leakage current RSTPD_N = 0.4 V 1- 1 A Ci input capacitance - 2.5 pF CL load capacitance - - 30 pF tr rise time of both SDA and SCL signals [3] 20 - 300 ns tf fall time of both SDA and SCL signals [3] 20 - 300 ns |
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