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M58LT128GS Datasheet(PDF) 17 Page - STMicroelectronics |
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M58LT128GS Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 98 page  M58LT128GST, M58LT128GSB 3 Bus operations 17/98 3.6 Reset During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. Table 3. Bus Operations Operation(1) 1. X = Don't care. E G W L RP WAIT(2) 2. WAIT signal polarity is configured using the Set Configuration Register command. DQ15-DQ0 Bus Read VIL VIL VIH VIH VIH Data Output Bus Write VIL VIH VIL VIH VIH Data Input Address Latch VIL VIH X VIL VIH Address Input Output Disable VIL VIH VIH VIH VIH Hi-Z Standby VIH XX X VIH Hi-Z Hi-Z Reset X X X X VIL Hi-Z Hi-Z |
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