TMS320VC5502 datasheet(3/195 Pages) TI1

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Contents

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166K – APRIL 2001 – REVISED NOVEMBER 2008

Revision History

........................................................................................................................... 2

TMS320VC5502

................................................................................................................. 15

1.1

Features

..................................................................................................................... 15

Introduction

....................................................................................................................... 16

2.1

Description

.................................................................................................................. 16

2.2

Pin Assignments

............................................................................................................ 17

2.2.1

Ball Grid Array (GZZ and ZZZ)

................................................................................ 17

2.2.2

Low-Profile Quad Flatpack (PGF)

............................................................................. 19

2.2.3

Signal Descriptions

.............................................................................................. 21

Functional Overview

........................................................................................................... 33

3.1

Memory

...................................................................................................................... 34

3.1.1

On-Chip ROM

................................................................................................... 34

3.1.2

On-Chip Dual-Access RAM (DARAM)

........................................................................ 35

3.1.3

Instruction Cache

................................................................................................ 35

3.1.4

Memory Map

..................................................................................................... 36

3.1.5

Boot Configuration

............................................................................................... 37

3.2

Peripherals

.................................................................................................................. 37

3.3

Configurable External Ports and Signals

................................................................................ 38

3.3.1

Parallel Port Mux

................................................................................................ 38

3.3.2

Host Port Mux

.................................................................................................... 39

3.3.3

Serial Port 2 Mux

................................................................................................ 40

3.3.4

External Bus Selection Register (XBSR)

..................................................................... 41

3.4

Configuration Examples

................................................................................................... 43

3.5

Timers

........................................................................................................................ 44

3.5.1

Timer Interrupts

.................................................................................................. 45

3.5.2

Timer Pins

........................................................................................................ 46

3.5.3

Timer Signal Selection Register (TSSR)

..................................................................... 47

3.6

Universal Asynchronous Receiver/Transmitter (UART)

............................................................... 48

3.7

Inter-Integrated Circuit (I

2C) Module

..................................................................................... 50

3.8

Host-Port Interface (HPI)

.................................................................................................. 51

3.9

Direct Memory Access (DMA) Controller

................................................................................ 52

3.9.1

DMA Channel 0 Control Register (DMA_CCR0)

........................................................... 52

3.10

System Clock Generator

.................................................................................................. 54

3.10.1

Input Clock Source

.............................................................................................. 55

3.10.1.1

Internal System Oscillator With External Crystal

................................................ 55

3.10.1.2

Clock Generation With PLL Disabled (Bypass Mode, Default)

................................ 56

3.10.1.3

Clock Generation With PLL Enabled (PLL Mode)

.............................................. 56

3.10.1.4

Frequency Ranges for Internal Clocks

........................................................... 57

3.10.2

Clock Groups

..................................................................................................... 57

3.10.2.1

C55x Subsystem Clock Group

.................................................................... 57

3.10.2.2

Fast Peripherals Clock Group

..................................................................... 57

3.10.2.3

Slow Peripherals Clock Group

.................................................................... 57

3.10.2.4

External Memory Interface Clock Group

......................................................... 58

3.10.3

EMIF Input Clock Selection

.................................................................................... 58

3.10.4

Changing the Clock Group Frequencies

..................................................................... 58

3.10.4.1

C55x Subsystem Clock Group

.................................................................... 59

3.10.4.2

Fast Peripherals Clock Group

..................................................................... 60

3.10.4.3

Slow Peripherals Clock Group

.................................................................... 60

3.10.4.4

External Memory Interface Clock Group

......................................................... 60

3.10.5

PLL Control Registers

.......................................................................................... 60

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TMS320VC5502 Datasheet(PDF) 3 Page - Texas Instruments

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