TMS320VC5502 datasheet(8/195 Pages) TI1

8 / 195 page

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166K – APRIL 2001 – REVISED NOVEMBER 2008

www.ti.com

3-37

Parallel GPIO Enable Register 1 Layout (0x4403)

........................................................................... 92

3-38

Parallel GPIO Direction Register 1 Layout (0x4404)

......................................................................... 93

3-39

Parallel GPIO Data Register 1 Layout (0x4405)

.............................................................................. 94

3-40

Parallel GPIO Enable Register 2 Layout (0x4406)

........................................................................... 95

3-41

Parallel GPIO Direction Register 2 Layout (0x4407)

......................................................................... 96

3-42

Parallel GPIO Data Register 2 Layout (0x4408)

.............................................................................. 97

3-43

External Bus Control Register Layout (0x8800)

............................................................................... 99

3-44

XPORT Configuration Register Layout (0x0100)

............................................................................ 101

3-45

XPORT Bus Error Register Layout (0x0102)

................................................................................ 102

3-46

DPORT Configuration Register Layout (0x0200)

............................................................................ 103

3-47

DPORT Bus Error Register Layout (0x0202)

................................................................................ 103

3-48

IPORT Bus Error Register Layout (0x0302)

................................................................................. 104

3-49

System Configuration Register Layout (0x07FD)

........................................................................... 105

3-50

Time-Out Control Register Layout (0x9000)

................................................................................. 106

3-51

IFR0, IER0, DBIFR0, and DBIER0 Registers Layout

....................................................................... 124

3-52

IFR1, IER1, DBIFR1, and DBIER1 Registers Layout

....................................................................... 124

3-53

Bad TCK Transition

............................................................................................................. 125

3-54

Good TCK Transition

............................................................................................................ 126

3-55

Sample Noise Filtering Circuitry

............................................................................................... 126

5-1

3.3-V Test Load Circuit

......................................................................................................... 132

5-2

Internal System Oscillator With External Crystal

............................................................................ 133

5-3

Bypass Mode Clock Timings

................................................................................................... 135

5-4

External Multiply-by-N Clock Timings

......................................................................................... 136

5-5

ECLKIN Timings for EMIF

...................................................................................................... 138

5-6

ECLKOUT1 Timings for EMIF Module

........................................................................................ 138

5-7

ECLKOUT2 Timings for EMIF Module

........................................................................................ 138

5-8

Asynchronous Memory Read Timings

........................................................................................ 140

5-9

Asynchronous Memory Write Timings

........................................................................................ 141

5-10

Programmable Synchronous Interface Read Timings (With Read Latency = 2)

........................................ 143

5-11

Programmable Synchronous Interface Write Timings (With Write Latency = 0)

........................................ 144

5-12

Programmable Synchronous Interface Write Timings (With Write Latency = 1)

........................................ 144

5-13

SDRAM Read Command (CAS Latency 3)

.................................................................................. 146

5-14

SDRAM Write Command

....................................................................................................... 146

5-15

SDRAM ACTV Command

...................................................................................................... 147

5-16

SDRAM DCAB Command

...................................................................................................... 147

5-17

SDRAM DEAC Command

...................................................................................................... 148

5-18

SDRAM REFR Command

...................................................................................................... 148

5-19

SDRAM MRS Command

....................................................................................................... 149

5-20

SDRAM Self-Refresh Timings

................................................................................................. 149

5-21

EMIF.HOLD/HOLDA Timings

.................................................................................................. 150

5-22

Reset Timings

.................................................................................................................... 152

List of Figures

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