TMS320VC5502 datasheet(4/195 Pages) TI1

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166K – APRIL 2001 – REVISED NOVEMBER 2008

www.ti.com

3.10.5.1

PLL Control / Status Register (PLLCSR)

........................................................ 61

3.10.5.2

PLL Multiplier Control Register (PLLM)

.......................................................... 62

3.10.5.3

PLL Divider 0 Register (PLLDIV0) (Prescaler)

.................................................. 63

3.10.5.4

PLL Divider1 Register (PLLDIV1) for SYSCLK1

................................................ 64

3.10.5.5

PLL Divider2 Register (PLLDIV2) for SYSCLK2

................................................ 65

3.10.5.6

PLL Divider3 Register (PLLDIV3) for SYSCLK3

................................................ 66

3.10.5.7

Oscillator Divider1 Register (OSCDIV1) for CLKOUT3

........................................ 66

3.10.5.8

Oscillator Wakeup Control Register (WKEN)

.................................................... 68

3.10.5.9

CLKOUT3 Select Register (CK3SEL)

............................................................ 69

3.10.5.10

CLKOUT Selection Register (CLKOUTSR)

.................................................... 70

3.10.5.11

Clock Mode Control Register (CLKMD)

........................................................ 70

3.10.6

Reset Sequence

................................................................................................. 71

3.11

Idle Control

.................................................................................................................. 71

3.11.1

Clock Domains

................................................................................................... 72

3.11.2

IDLE Procedures

................................................................................................ 72

3.11.2.1

CPU Domain Idle Procedure

...................................................................... 72

3.11.2.2

Master Port Domain (DMA/HPI) Idle Procedure

................................................ 72

3.11.2.3

Peripheral Modules Idle Procedure

............................................................... 72

3.11.2.4

EMIF Module Idle Procedure

...................................................................... 73

3.11.2.5

IDLE2 Mode

.......................................................................................... 73

3.11.2.6

IDLE3 Mode

.......................................................................................... 73

3.11.2.7

IDLE3 Mode With Internal Oscillator Disabled

.................................................. 73

3.11.3

Module Behavior at Entering IDLE State

..................................................................... 74

3.11.4

Wake-Up Procedure

............................................................................................ 75

3.11.4.1

CPU Domain Wake-up Procedure

................................................................ 75

3.11.4.2

Master Port Domain (DMA/HPI) Wake-up Procedure

.......................................... 75

3.11.4.3

Peripheral Modules Wake-up Procedure

........................................................ 75

3.11.4.4

EMIF Module Wake-up Procedure

................................................................ 76

3.11.4.5

IDLE2 Mode Wake-up Procedure

................................................................. 76

3.11.4.6

IDLE3 Mode Wake-up Procedure

................................................................. 76

3.11.4.7

IDLE3 Mode With Internal Oscillator Disabled Wake-up Procedure

......................... 76

3.11.4.8

Summary of Wake-up Procedures

................................................................ 77

3.11.5

Auto-Wakeup/Idle Function for McBSP and DMA

........................................................... 77

3.11.6

Clock State of Multiplexed Modules

........................................................................... 77

3.11.7

IDLE Control and Status Registers

............................................................................ 78

3.11.7.1

IDLE Configuration Register (ICR)

................................................................ 78

3.11.7.2

IDLE Status Register (ISTR)

....................................................................... 80

3.11.7.3

Peripheral IDLE Control Register (PICR)

........................................................ 81

3.11.7.4

Peripheral IDLE Status Register (PISTR)

........................................................ 84

3.11.7.5

Master IDLE Control Register (MICR)

............................................................ 85

3.11.7.6

Master IDLE Status Register (MISR)

............................................................. 86

3.12

General-Purpose I/O (GPIO)

............................................................................................. 86

3.12.1

General-Purpose I/O Port

...................................................................................... 86

3.12.1.1

General-Purpose I/O Direction Register (IODIR)

............................................... 87

3.12.1.2

General-Purpose I/O Data Register (IODATA)

.................................................. 87

3.12.2

Parallel Port General-Purpose I/O (PGPIO)

................................................................. 88

3.12.2.1

Parallel GPIO Enable Register 0 (PGPIOEN0)

................................................. 89

3.12.2.2

Parallel GPIO Direction Register 0 (PGPIODIR0)

.............................................. 90

3.12.2.3

Parallel GPIO Data Register 0 (PGPIODAT0)

.................................................. 91

3.12.2.4

Parallel GPIO Enable Register 1 (PGPIOEN1)

................................................. 92

3.12.2.5

Parallel GPIO Direction Register 1 (PGPIODIR1)

.............................................. 93

3.12.2.6

Parallel GPIO Data Register 1 (PGPIODAT1)

.................................................. 94

3.12.2.7

Parallel GPIO Enable Register 2 (PGPIOEN2)

................................................. 95

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